Ever heard of Chip Design Pentagon?

Hey There,

Know what Pentagon is? It is a plane figure which has 5-straight sides and 5-angles. For a perfect pentagon, it needs all its sides and angles to be the same, till the last decimal. Do you know what is the similarity between pentagon and our upcoming workshop “Advanced Physical Design workshop using OpenLANE/SKY130”?  Look above image and you would guess it right. It is a perfect blend of topics where even a fresher can jump-start his/her career in chip design in just 5-days

First day is dedicated to familiarization with OpenLANE and Sky130 PDK’s (which are real PDK’s), basic Physical design stages, design preparation stage and execution & analysis of synthesis

Second day will be introduction to floorplan phase, basic differences between LEF/DEF, introduction to special cells and execution & analysis of placement using OpenLANE toolchain

Third day is where we get to the core of VLSI with standard cell design using sky130 PDK, SPICE simulation in ngspice and standard cell characterization. Not just that, we also plug this hand-made standard cell into real design and check if it behaves the way its supposed to behave without disturbing existing flow

Fourth day is from bottom to top, with PNR using custom cell, clock tree synthesis (CTS), static timing analysis (STA) and ECO, all using custom cell which you have built on day 3

Finally, fifth day is dedicated to routing algorithms, triton-Route, SPEF extraction and post-layout STA using extracted spef and custom cells designed on Day 3

Doesn’t that sound perfect Pentagon? Atleast the last batch did find it as “Perfect Pentagon” and the name was suggested by one of the participants from previous batch

Really loved the name that was given to our workshops and hence thought of sharing this with you. Next chip design pentagon batch (25th Nov to 29th Nov) registration will close in 36hours and below link has all details.


Will see all of you enrolled participants on 25th November

All the best and happy learning

Posted in Concepts, Conference, Design, Floorplan, Google/SKywater130, IP design, Open Source, RISC-V, Static timing Analysis, Tool related, VSD Course, VSD Summer Internship, VSD-IAT, Webinar.

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