From online VLSI learning company to design company
VSD Talk on "Survey of E31 RISC-V Core Floor Plan and Its Impact on Power, Performance and Area PPA" @RISC-V workshop at IIT Madras...
Addressing a crowd of close to ~200 RISC-V enthusiasts’ people.It was really a pleasure talking about the latest developments in the world of open-source EDA and techniques we used to blend it with E31 RISC-V Core (from SiFive).
VLSI System Design Corp. Paper
Our company's first paper on IEEE explore for technology mediated learning - World's prestigious institute for engineering and technology innovation. Here's the link for the paper.
Kunal's Work @ IIT Bombay
Co-author of " A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems"
Project on "Process Optimization on Raith-150 TWO E-Beam Lithography Tool for sub-100nm CMOS device fabrication"
VSD @ ORConf 2017
Poster presented in ORConf 2017 "An automated C-to-GDS flow using open-source EDA tools for medium-sized SOC design and implementation"
Semicon China LIVE talk on vsdflow – An EDA Management System
Semicon China, March 2018
This video is our work on 'vsdflow' which was selected in Semicon China, March 2018.
"vsdflow" is an EDA Management System, which helps you to plug and play any EDA tool needed for IC design flow, and get the PPA chart for an RTL.
This flow helps lot of engineers to benchmark their own chain of tools to get best output. Currently, it is tested using all opensource tools. Part of the code can be downloaded from below page: https://www.vlsisystemdesign.com/proj...