IP by Interns – VLSI System Design

Name	University	Project Title	Tech Node	Github Link
Anmol Purty	M.tech from National Institute of Technology, Warangal	General Purpose bandgap	SKY130	https://github.com/vsdip/avsdbgp_3v3_sky130_v2
Harsh Shukla	MS Analog and Mixed Signal Design, Arizona State University	10 placeable Standard Cell library design, layout and characterization (just like inv design in workshop) with 4 drive strengths of each. Total 40 standard cells	SKY130	https://github.com/vsdip/vsdStdCellCharacterizer_sky130
Harshitha Basavaraju	PhD Scholar @ University of Bundeswehr, Munich, Germany	10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference	SKY130	https://github.com/vsdip/avsddac_3v3_sky130_v1
Malay Marut Das	EDI Analyst at Miracle Software Systems, Inc., Portland, Oregon, United States	Lower power current programmable CMOS comparator with hysteresis	SKY130	https://github.com/vsdip/avsdcmp_3v3_sky130
S Skandha Deepsita	PhD Scholar @ IIITDM Kancheepurama	10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference	SKY130	https://github.com/vsdip/avsddac_3v3_sky130_v1
Sameer S Durgoji	B.Tech (Electronics and Communication Engineering), National Institute of Technology Karnataka	10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference	SKY130	https://github.com/vsdip/avsddac_3v3_sky130_v2
Shalini Kanna	Master of Science in Computer Engineering, University of Massachusetts Lowell	10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference	SKY130	https://github.com/vsdip/avsddac_3v3_sky130_v1
Shon Pravin Taware	M.Tech. Embedded System and VLSI Design, Shri Guru Gobind Singhji Institute of Engineering and Technology, Vishnupuri, Nanded	OpenRAM configuration for SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns	SKY130	https://github.com/vsdip/vsdsram_sky130
Subham Mohapatra	Electrical & Electronics undergrad, NIT Karnataka	On-chip PLL (avsdpll_3v3) Clock multiplier (pll) (Fclkin – 5MHz to 12Mhz, Fclkout – 40MHz to 100MHz at 1.8v) characterization TCL flow for sky130 tt, ss, ff, sf, fs corners	SKY130	https://github.com/vsdip/avsdpll_1v8_sky130_ss
Swarup Pulujkar	Hardware Development Engineer at eZono AG, Germany	General Purpose bandgap	SKY130	https://github.com/vsdip/avsdbgp_3v3_sky130_v1https://github.com/vsdip/avsdbgp_3v3_sky130_v1

Name	University	Project Title	Tech Node	Github Link
OpenLANE based projects
Deepak Verma	IIIT Sonepat	Design of 4KB(1024*32) SRAM 1.8V with operating voltage 1.8v and access time < 2.5ns	SKY130	https://github.com/Deepak42074/vsdsram_sky130
Pradeepkumar S K	Kalpataru Institute of Technology, Tiptur, Karnataka	Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node	SKY130	https://github.com/pradeepsk13/vsdsram_sky130_1.8V
Roshan Khatri Luitel	Punjab University	PLL IP to be tested is included in the SOIC-24 package to communicate with external circuitry present in the testboard	SKY130	https://github.com/rsnkhatri3/vsdPLLSoC
Lakshmi S	Georgia Institute of Technology, USA	8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.	SKY130	https://github.com/lakshmi-sathi/avsdpll_1v8
RISC V
A RADHIKA	University of Hyderabad (UOH), Hyderabad	RISCV Developement Board	NIL	https://github.com/Kunal-Radhika/vsdDevBoard_v0

Name	University	Project Title	Tech Node	Github Link
OpenLANE based projects
Praharsha Mahurkar	Maharashtra Institute of Technology, Pune	OpenLANE RTL2GDS for mixed signal SoC (Inputs = mixed signal Verilog, OpenLANE RTL2GDS tools, outputs = GDSII)	SKY130	https://github.com/praharshapm/vsdmixedsignalflow
Nickson Jose	VSD Intern	Standard cell characterization flow using ngspice/Magic/OpenLANE	SKY130	https://github.com/nickson-jose/vsdstdcelldesign
Euler’s path generation
Sethupathi Balakrishnan	VSD Intern	Open-source Layout Generator (Inputs = Digital or Analog Circuit, Output = Layout)	OSU180	https://github.com/sethupathib/vsdGraphExtractor
SRAM (4kB) using OpenRAM
Yash Kumar	Fr. Conceicao Rodrigues College of Engineering, Mumbai	SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns (OpenRAM)	OSU180	https://github.com/yash-k99/vsdsram
Reuel Reuben	BVPCOE, Mumbai	SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns (OpenRAM)	OSU180	https://github.com/ReuelReuben/vsdSRAM
Penumarthi Aishwarya	NIT Jamshedpur	SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns (OpenRAM)	OSU180	https://github.com/aishwaryapenumarthi/VSDSRAM
On-chip 8x clock multiplier
Paras Sanjay Gidd	Manipal Institute of Technology,(MAHE)	On-chip Clock multiplier (pll) (Fclkin – 5MHz to 12Mhz, Fclkout – 40MHz to 100MHz at 1.8v	OSU180	https://github.com/parasgidd/avsdpll_3v3/
Abel Joseph John	NSS College of Engineering, Palakkad	On-chip Clock multiplier (pll) (Fclkin – 5MHz to 12Mhz, Fclkout – 40MHz to 100MHz at 1.8v		https://github.com/eddygta17/avsdpll_3v3
10-bit DAC
Ashutosh Sharma	IIITD&M Kurnool	10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference	OSU180	https://github.com/xzlashutosh/avsddac_3v3
Neethu Johny	B.M.S College of Engineering, Bangalore	10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference		https://github.com/neethujohny/avsddac_3v3
10-bit ADC
Sheryl Corina Serrao	Fr. Conceicao Rodrigues College of Engineering, Mumbai	10-bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference	OSU180	https://github.com/ADC-TEAM2020/avsdadc_3v3
V.UDAY	Siddhartha Institute Of Technology	10-bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference	OSU180
Shalini Priya	NIT Jamshedpur	10-bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference	OSU180
Ananya Ghorai	IIT(ISM) Dhanbad	Comparator part of ADC	OSU180

NAME	UNIVERSITY/INSTITUE	PROJECT TITLE	TECH NODE	GITHUB LINK
Ankur Sah	National Institute of Technology, Jamshedpur	General purpose band-gap reference with N-well resistors at VDD=3.3v, Vbgp=1.2v	OSU018	https://github.com/ankursah5/avsdbgp_3v3
Anusha R	Visveswaraya Technological University(VTU)	6T-SRAM cell	OSU018	https://github.com/Anushar123/vsdsram
Bellana Avinash Naidu	NATIONAL INSTITUTE OF TECHNOLOGY, ROURKELA	10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference@osu180nm	OSU018	https://github.com/VSD-DACteam/avsddac_3v3
Charu Gupta	DTU, Delhi	Open-source Power analysis tool - average switching power and leakage power using Python engine	OSU018	https://github.com/CharuGupta-eng/vsdOSPowerCalc
Jayasri Veeravilli	SRM University	10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference@osu180nm	OSU018	https://github.com/VSD-DACteam/avsddac_3v3
Nalla Gowthami	National Institute of Technology Rourkela	Bi-directional Buffer with Non-Inverting CMOS Input and Gated Pull-down and Pull-up	OSU018	https://github.com/gowthaminalla/vsdbbcud4f
Neelam Buddhiram Chaurasiya	Mumbai University	10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference@osu180nm	OSU018	https://github.com/VSD-DACteam/avsddac_3v3
Prithivi Raj K	National Institute Of Technology, Tiruchirapalli	4-input &2-input, 1-output 3.3V analog multiplexer with 1.8V digital select line@osu180nm	OSU018	https://github.com/prithivjp/avsdmux4x1_3v3 https://github.com/prithivjp/avsdmux2x1_3v3
Sheryl Corina Serrao	Mumbai University	General purpose band-gap reference with N-well resistors at VDD=3.3v, Vbgp=1.2v	OSU018	https://github.com/sherylcorina/avsdbgp_3v3
Tanvi Arora	Deenbandhu Chhotu Ram University of Science and Technology,Murthal,Sonipat	Bi-directional Buffer with Non-Inverting CMOS Input and Gated Pull-down and Pull-up	OSU018	https://github.com/tanviarora23/vsdbbcud4f
YALAMANCHILI VAHINI	NIT JAMSHEDPUR	Open-source Power analysis tool - average switching power and leakage power using TCL engine	OSU018	https://github.com/yalamanchilivahini5/vsdtclpowertool

Open-source Semiconductor IP's designed by VSD Community

IP Catalogue (yet to be Silicon proven)- Specs released under APACHE LICENSE 2.0

VSD Online IP Research Internship 4th Batch

VSD Online IP Research Internship 3rd Batch

VSD Online IP Research Internship 2nd Batch

VSD Online IP Research Internship 1st Batch

Refer below link to know more about VSD-IAT workshops and future internships: