Open-source Silicon IP's designed by VSD Community

VSDFLOW (VLSI System Design Flow)

An automated RTL2GDS open-source flow

vsdflow is a `plug and play (PnP)' EDA management system, built for chip designers to implement their ideas and convert to GDSII. `plug and play (PnP)' refers to switching between any EDA tools, for e.g. user can plug Cadence Genus for synthesis, Synopsys ICC for PNR and Tempus for sign-off STA.

https://github.com/kunalg123/vsdflow

vsdflow

avsdadc_3v3

10 bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

Circuit to Layout

Open-source Layout Generator

avsdcmp_3v3

Lower power current programmable CMOS comparator with hysteresis

avsdxtosc_3v3

Crystal oscillator analog pads (3.3V, Fclkout-1MHz-4MHz

avsddac_3v3

10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

avsdbgp_3v3

General purpose Bandgap

vsdbbcud4f

Bi-directional Buffer with Non-Inverting CMOS Input and Gated Pull-down and Pull-up, Strength 4mA @ 3.3V, Normal, High noise (Fast speed)

PowerAnalysisMethodology

Open-source Power Calculator

mem4kBytesOr32kbitsSpec

SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns

avsdpll_3v3

On-chip Clock multiplier (pll) (Fclkin – 5MHz to 12Mhz, Fclkout – 40MHz to 100MHz at 1.8v