Open-source Semiconductor IP's designed by VSD Community

IP Catalogue (yet to be Silicon proven)- Specs released under APACHE LICENSE 2.0

VSD Online IP Research Internship 4th Batch

Name

University

Project Title

Tech Node

Github Link

Anmol Purty

M.tech from National Institute of Technology, Warangal

General Purpose bandgap

SKY130

Harsh Shukla

MS Analog and Mixed Signal Design, Arizona State University

10 placeable Standard Cell library design, layout and characterization (just like inv design in workshop) with 4 drive strengths of each. Total 40 standard cells

SKY130

Harshitha Basavaraju

PhD Scholar @ University of Bundeswehr, Munich, Germany

10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

SKY130

Malay Marut Das

EDI Analyst at Miracle Software Systems, Inc., Portland, Oregon, United States

Lower power current programmable CMOS comparator with hysteresis

SKY130

S Skandha Deepsita

PhD Scholar @ IIITDM Kancheepurama

10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

SKY130

Sameer S Durgoji

B.Tech (Electronics and Communication Engineering), National Institute of Technology Karnataka

10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

SKY130

Shalini Kanna

Master of Science in Computer Engineering, University of Massachusetts Lowell

10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

SKY130

Shon Pravin Taware

M.Tech. Embedded System and VLSI Design, Shri Guru Gobind Singhji Institute of Engineering and Technology, Vishnupuri, Nanded

OpenRAM configuration for SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns

SKY130

Subham Mohapatra

Electrical & Electronics undergrad, NIT Karnataka

On-chip PLL (avsdpll_3v3) Clock multiplier (pll) (Fclkin – 5MHz to 12Mhz, Fclkout – 40MHz to 100MHz at 1.8v) characterization TCL flow for sky130 tt, ss, ff, sf, fs corners

SKY130

Swarup Pulujkar

Hardware Development Engineer at eZono AG, Germany

General Purpose bandgap

SKY130

VSD Online IP Research Internship 3rd Batch

Name

University

Project Title

Tech Node

Github Link

OpenLANE based projects

Deepak Verma

IIIT Sonepat

Design of 4KB(1024*32) SRAM 1.8V with operating voltage 1.8v and access time < 2.5ns

SKY130

Pradeepkumar S K

Kalpataru Institute of Technology, Tiptur, Karnataka

Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node

SKY130

Roshan Khatri Luitel

Punjab University

PLL IP to be tested is included in the SOIC-24 package to communicate with external circuitry present in the testboard

SKY130

Lakshmi S

Georgia Institute of Technology, USA

8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

SKY130

RISC V

A RADHIKA

University of Hyderabad (UOH), Hyderabad

RISCV Developement Board

NIL

VSD Online IP Research Internship 2nd Batch

Name

University

Project Title

Tech Node

Github Link

OpenLANE based projects

Praharsha Mahurkar

Maharashtra Institute of Technology, Pune

OpenLANE RTL2GDS for mixed signal SoC (Inputs = mixed signal Verilog, OpenLANE RTL2GDS tools, outputs = GDSII)

SKY130

Nickson Jose

VSD Intern

Standard cell characterization flow using ngspice/Magic/OpenLANE

SKY130

Euler’s path generation

Sethupathi Balakrishnan

VSD Intern

Open-source Layout Generator (Inputs = Digital or Analog Circuit, Output = Layout)

OSU180

SRAM (4kB) using OpenRAM

Yash Kumar

Fr. Conceicao Rodrigues College of Engineering, Mumbai

SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns (OpenRAM)

OSU180

Reuel Reuben

BVPCOE, Mumbai

SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns (OpenRAM)

OSU180

Penumarthi Aishwarya

NIT Jamshedpur

SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns (OpenRAM)

OSU180

On-chip 8x clock multiplier

Paras Sanjay Gidd

Manipal Institute of Technology,(MAHE)

On-chip Clock multiplier (pll) (Fclkin – 5MHz to 12Mhz, Fclkout – 40MHz to 100MHz at 1.8v

OSU180

Abel Joseph John

NSS College of Engineering, Palakkad

On-chip Clock multiplier (pll) (Fclkin – 5MHz to 12Mhz, Fclkout – 40MHz to 100MHz at 1.8v

10-bit DAC

Ashutosh Sharma

IIITD&M Kurnool

10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

OSU180

Neethu Johny

B.M.S College of Engineering, Bangalore

10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

10-bit ADC

Sheryl Corina Serrao

Fr. Conceicao Rodrigues College of Engineering, Mumbai

10-bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

OSU180

V.UDAY

Siddhartha Institute Of Technology

10-bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

OSU180

Shalini Priya

NIT Jamshedpur

10-bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

OSU180

Ananya Ghorai

IIT(ISM) Dhanbad

Comparator part of ADC

OSU180

VSD Online IP Research Internship 1st Batch

NAME

UNIVERSITY/INSTITUE

PROJECT TITLE

TECH NODE

GITHUB LINK

Ankur Sah

National Institute of Technology, Jamshedpur

General purpose band-gap reference with N-well resistors at VDD=3.3v, Vbgp=1.2v

OSU018

Anusha R

Visveswaraya Technological University(VTU)

6T-SRAM cell

OSU018

Bellana Avinash Naidu

NATIONAL INSTITUTE OF TECHNOLOGY, ROURKELA
10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference@osu180nm

OSU018

Charu Gupta

DTU, Delhi

Open-source Power analysis tool - average switching power and leakage power using Python engine

OSU018

Jayasri Veeravilli

SRM University

10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference@osu180nm

OSU018

Nalla Gowthami

National Institute of Technology Rourkela

Bi-directional Buffer with Non-Inverting CMOS Input and Gated Pull-down and Pull-up

OSU018

Neelam Buddhiram Chaurasiya

Mumbai University 

10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference@osu180nm

OSU018

Prithivi Raj K

National Institute Of Technology, Tiruchirapalli

4-input &2-input, 1-output 3.3V analog multiplexer with 1.8V digital select line@osu180nm

OSU018

Sheryl Corina Serrao

Mumbai University

General purpose band-gap reference with N-well resistors at VDD=3.3v, Vbgp=1.2v

OSU018

Tanvi Arora

Deenbandhu Chhotu Ram University of Science and Technology,Murthal,Sonipat

Bi-directional Buffer with Non-Inverting CMOS Input and Gated Pull-down and Pull-up

OSU018

YALAMANCHILI VAHINI

NIT JAMSHEDPUR

Open-source Power analysis tool - average switching power and leakage power using TCL engine

OSU018

Refer below link to know more about VSD-IAT workshops and future internships:

VSD – IAT