Open-source Semiconductor IP's designed by VSD Community

IP Catalogue (yet to be Silicon proven)- Specs released under APACHE LICENSE 2.0

VSD Online IP Research Internship 2nd Batch

Name

University

Project Title

Tech Node

Github Link

OpenLANE based projects

Praharsha Mahurkar

Maharashtra Institute of Technology, Pune

OpenLANE RTL2GDS for mixed signal SoC (Inputs = mixed signal Verilog, OpenLANE RTL2GDS tools, outputs = GDSII)

SKY130

Nickson Jose

VSD Intern

Standard cell characterization flow using ngspice/Magic/OpenLANE

SKY130

Euler’s path generation

Sethupathi Balakrishnan

VSD Intern

Open-source Layout Generator (Inputs = Digital or Analog Circuit, Output = Layout)

OSU180

SRAM (4kB) using OpenRAM

Yash Kumar

Fr. Conceicao Rodrigues College of Engineering, Mumbai

SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns (OpenRAM)

OSU180

Reuel Reuben

BVPCOE, Mumbai

SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns (OpenRAM)

OSU180

Penumarthi Aishwarya

NIT Jamshedpur

SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns (OpenRAM)

OSU180

On-chip 8x clock multiplier

Paras Sanjay Gidd

Manipal Institute of Technology,(MAHE)

On-chip Clock multiplier (pll) (Fclkin – 5MHz to 12Mhz, Fclkout – 40MHz to 100MHz at 1.8v

OSU180

Abel Joseph John

NSS College of Engineering, Palakkad

On-chip Clock multiplier (pll) (Fclkin – 5MHz to 12Mhz, Fclkout – 40MHz to 100MHz at 1.8v

10-bit DAC

Ashutosh Sharma

IIITD&M Kurnool

10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

OSU180

Neethu Johny

B.M.S College of Engineering, Bangalore

10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

10-bit ADC

Sheryl Corina Serrao

Fr. Conceicao Rodrigues College of Engineering, Mumbai

10-bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

OSU180

V.UDAY

Siddhartha Institute Of Technology

10-bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

OSU180

Shalini Priya

NIT Jamshedpur

10-bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

OSU180

Ananya Ghorai

IIT(ISM) Dhanbad

Comparator part of ADC

OSU180

VSD Online IP Research Internship 1st Batch

NAME

UNIVERSITY/INSTITUE

PROJECT TITLE

TECH NODE

GITHUB LINK

Ankur Sah

National Institute of Technology, Jamshedpur

General purpose band-gap reference with N-well resistors at VDD=3.3v, Vbgp=1.2v

OSU018

Anusha R

Visveswaraya Technological University(VTU)

6T-SRAM cell

OSU018

Bellana Avinash Naidu

NATIONAL INSTITUTE OF TECHNOLOGY, ROURKELA
10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference@osu180nm

OSU018

Charu Gupta

DTU, Delhi

Open-source Power analysis tool - average switching power and leakage power using Python engine

OSU018

Jayasri Veeravilli

SRM University

10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference@osu180nm

OSU018

Nalla Gowthami

National Institute of Technology Rourkela

Bi-directional Buffer with Non-Inverting CMOS Input and Gated Pull-down and Pull-up

OSU018

Neelam Buddhiram Chaurasiya

Mumbai University 

10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference@osu180nm

OSU018

Prithivi Raj K

National Institute Of Technology, Tiruchirapalli

4-input &2-input, 1-output 3.3V analog multiplexer with 1.8V digital select line@osu180nm

OSU018

Sheryl Corina Serrao

Mumbai University

General purpose band-gap reference with N-well resistors at VDD=3.3v, Vbgp=1.2v

OSU018

Tanvi Arora

Deenbandhu Chhotu Ram University of Science and Technology,Murthal,Sonipat

Bi-directional Buffer with Non-Inverting CMOS Input and Gated Pull-down and Pull-up

OSU018

YALAMANCHILI VAHINI

NIT JAMSHEDPUR

Open-source Power analysis tool - average switching power and leakage power using TCL engine

OSU018

VSD IP Specs Sheet

avsdadc_3v3

10 bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

Circuit to Layout

Open-source Layout Generator

avsdcmp_3v3

Lower power current programmable CMOS comparator with hysteresis

avsdxtosc_3v3

Crystal oscillator analog pads (3.3V, Fclkout-1MHz-4MHz

avsddac_3v3

10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

avsdbgp_3v3

General purpose Bandgap

avsdpll_3v3

On-chip Clock multiplier (pll) (Fclkin – 5MHz to 12Mhz, Fclkout – 40MHz to 100MHz at 1.8v

vsdbbcud4f

Bi-directional Buffer with Non-Inverting CMOS Input and Gated Pull-down and Pull-up, Strength 4mA @ 3.3V, Normal, High noise (Fast speed)

PowerAnalysisMethodology

Open-source Power Calculator

mem4kBytesOr32kbitsSpec

SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns

VSDFLOW (VLSI System Design Flow)

An automated RTL2GDS open-source flow

vsdflow is a `plug and play (PnP)' EDA management system, built for chip designers to implement their ideas and convert to GDSII. `plug and play (PnP)' refers to switching between any EDA tools, for e.g. user can plug Cadence Genus for synthesis, Synopsys ICC for PNR and Tempus for sign-off STA.

https://github.com/kunalg123/vsdflow

vsdflow
vsdflow