13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core

A great Blog and an inspirational story by Steve Hoover – Thanks Steve for giving permission to share this one
Hey There, from Steve Hoover, Founder, Redwood EDA

One of my great pleasures operating my EDA startup, Redwood EDA, is working with enthusiastic college students and open-source developers and seeing how our technology is renewing excitement for logic design. Recently, Kunal Ghosh of VLSI System Design and I conducted our third “Microprocessor for You in Thirty Hours” (MYTH) Workshop, where participants learn about RISC-V and build their own RISC-V CPU cores (something that’s typically done over the course of a semester or two). In addition to reaching graduate students and professionals, one of our goals with the workshop is to give students an opportunity to learn logic design earlier in their education–like, say, as a college freshman or sophomore. So just imagine our surprise when Nicholas introduced himself in the chat forum of our workshop.

This was a real test of our goals. It was also a real testament to Nicholas’s thirst for knowledge and the outside-the-box thinking of his home-schooling parents, Rasa and Mike. Having a 13-year-old of my own, I was particularly impressed by Nicholas’s willingness to put himself out there, asking questions and joining Zoom calls (not to mention his familiarity with Linux). I’ve since learned that Nicholas has been awarded in spelling bees and math competitions and is an expert at solving the Rubik’s Cube. Somehow, I’m not surprised.

Admittedly, the workshop was a stretch for Nicholas and, for him, did not live up to its 30-hour claim. At the close of the workshop, he had gotten a little more than halfway through. He had learned about the RISC-V ISA and compilation tools; he had developed circuit design skills; he had created a pipelined calculator circuit; and his first RISC-V CPU was showing signs of life. We considered this a great success!

But Nicholas, after working five long days straight in the workshop, still had the stamina to see his project through. (Note that when I suggest to my own sons that they design a circuit with me, it tends to be viewed as more of a homework assignment, and I’m lucky if they spend an hour with me.) Normally, when the workshop ends, we shut it down, and work stops, but we agreed to a bit of special treatment, and Nicholas kept at it in the evenings, after returning to his normal schooling.

Given his enthusiasm, I figured Nicholas would at least be able to get through the day-4 content and see his non-pipelined CPU summing numbers from 1 to 9. That would even be blog-worthy. With continued online chatter and a Zoom call or two, he did complete the day-4 CPU!

Day 5, on the other hand, would be a bit much to ask. Day 5 is where we really see how well students absorbed what they were taught during days 1-4. On day 5, students are asked to pipeline their CPU, dealing with various pipeline hazards. That’s a bit hard-core for a 13-year-old, right?

Having reviewed his work and discussed it with him, I’m happy to say that Nicholas has indeed successfully completed his 5-stage pipelined RISC-V CPU core and will be getting his certificate soon!

When I asked about his experience, he responded (perhaps with a bit of parental oversight) “I enjoyed the challenge very much, and it has gotten me excited about RISC-V and digital design.” He also expressed his gratitude to Shivam Potdar and the rest of the MYTH Workshop crew.

Hats off to you, young Nicholas, circuit designer extraordinaire. Keep thirsting for knowledge. It will take you far!

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The 4th run of the MYTH Workshop starts December 2nd. I would not necessarily recommend signing up your children, but if you are interested in participating, we would love for you to join us. Just be aware that, if you do sign up, the pressure is on. You would not want to be outdone by a middle-schooler. Or… perhaps you already have and need to catch up ;). Also, be on the lookout for similar training from RISC-V Learn Online, coming soon!

Registration for Ethical RISC-V IoT Workshop

Welcome to Ethical RISC-V IoT Workshop

The “Ethical RISC-V IoT Workshop” at IIIT Bangalore, organized in collaboration with VSD, is a structured, educational competition aimed at exploring real-world challenges in IoT and embedded systems. Participants progress through three stages: building an application, injecting and managing faults, and enhancing application security. The event spans from May 9 to June 15, 2024, culminating in a showcase of top innovations and an award ceremony. This hands-on hackathon emphasizes learning, testing, and securing applications in a collaborative and competitive environment.

Rules :
  1. Only for Indian Student whose college is registered under VTU
  2. Only team of 2 members can Register
  3. Use only VSDSquadron Mini resources for product development
Awards :
  1. Prize money for final 10 Team
  2. 3 Winner team’s Product will be evaluated for Incubation
  3. 7 consolation prizes
  4. Completion Certificate to final round qualifier
  5. Chance to build a Proud Secured RISC-V Platform for India

Date for Registration : 9th May - 22nd May, 2024
Hackathon Inauguration : 23rd May 2024

VSDSquadron (Educational Board)

VSDSquadron, a cutting-edge development board based on the RISC-V architecture that is fully open-source. This board presents an exceptional opportunity for individuals to learn about RISC-V and VLSI chip design utilizing only open-source tools, starting from the RTL and extending all the way to the GDSII. The possibilities for learning and advancement with this technology are limitless.

Furthermore, the RISC-V chips on these boards should be open for VLSI chip design learning, allowing you to explore PNR, standard cells, and layout design. And guess what? vsdsquadron is the perfect solution for all your needs! With its comprehensive documentation and scalable labs, thousands of students can learn and grow together.

VSD HDP (Hardware Design Program) Duration-10 Week

With VSD Hardware Design Program (VSD-HDP),  you have the opportunity to push the boundaries of what exist in open source and establish the new benchmark for tomorrow.

It will leverage your degree in Electrical or Computer Engineering to work with

  • Programmable logic
  • Analog/ digital IP
  • RISC-V
  • Architecture & microprocessors
  • ASICs and SoCs on high-density digital or RF circuit cards
  • Gain hands-on knowledge during design validation and system integration.

Sounds exciting to just get started with expert mentors, doesn’t it? But we are looking for the next generation of learners, inventors, rebels, risk takers, and pioneers.

“Spend your summer working in the future !!”

Outcomes of VSD Online Research IP Design Internship Program

  1. Job opportunities in Semiconductor Industry
  2. Research work can be submitted to VLSI International journals
  3. Participate in Semiconductor International Conference with Internship Research Work
  4. Paper Publications in IEEE Conference and SIG groups
  5. Tape out opportunity and IP Royalty
  6. Interact with world class Semiconductor designer and researchers
  7. Academic professions where more research projects are encouraged.
  8. All the above research and publication work will help colleges and institutes to improve accreditation levels.

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VSD – Intelligent Assessment Technology (VSD-IAT)

VSD – Intelligent Assessment Technology (VSD-IAT) is expertly built training platform and is suited for designer requirements. Semiconductor companies understand the value of training automation and Engineer performance enhancement, and do not need to be convinced of the impact of a virtual platform for learning. VSD trainings are quick, relevant, and easy to access from any device at any time zone.

VSD Intern Webinars

VSD Interns made it happen !!

VSD is working towards creating innovative talent pool who are ready to develop design and products for the new tech world. VSD believes in “Learning by doing principle” , and always prepare the student to apply the knowledge learned in the workshops, webinars and courses. We always push our students to work on new designs, test it and work continuously till it becomes the best performing design. Any student who enrolls to VSD community starts working with small design and grows with us and develops a tapeout level design with complete honesty and dedication towards the Work !!

Check out VSD Interns Achievement!

VSDOpen Online Conference

Welcome to the World’s only online conference in Semiconductor Industry VSDOpen Conference. With enormous support and global presence of audience from different segments of industrial lobby and academia made a highly successful event. Evolution is change in the genetic makeup of a population over time, online conference is one kind evaluation everyone adapt soon. 

  • VSDOpen 2022 is an online conference to share open-source research with the community and promote  hardware design mostly done by the student community.
  • VSDOpen 2022 is based on the theme “How to lower the cost to learn, build, and tapeout chips ?”  , which will provide a platform to community to build stronger designs and strengthen the future of Chip design.
  • VSDOpen is envisioned to create a community based revolution in semiconductor hardware technology.
  • The open source attitude is required to bring out the talent and innovation from the community who are in remote part of world and have least access to the technologies.  And now Google support will help to bring the vision to execution by VSD team

VSD Online Course by Kunal Ghosh

VSD offers online course in complete spectrum of vlsi backend flow from RTL design, synthesis and Verification, SoC planning and design, Sign-off analysis, IP Design, CAD/EDA automation and basic UNIX/IT, Introduction to latest technology – RISC-V, Machine intelligence in EDA/CAD, VLSI Interview FAQ’s.

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