India, the land of innovations and revolutions, is on the brink of another technological metamorphosis. And you, the young minds of our great nation, are […]
Read our interview at Electronics for you (EFY) magazine and dive into the transformative world of VLSI with the enlightening article that serves as a beacon for all aspiring electronics enthusiasts. VLSI, or Very Large Scale Integration, isn’t just a technical term; it’s a vision that beckons the future of electronics, breathing life into devices by embedding millions of transistors on a singular chip. This incredible feat of engineering has not only redefined the electronics landscape but has also expanded the horizons of what’s conceivable.
The VSDSquadron educational board provides a unique opportunity for learners to gain hands-on experience in electronics system design and chip design. The board’s open-source nature allows for easy access to IPs, PDKs, and tools, including RISC-V, providing learners with a complete and comprehensive curriculum in these areas. With the board’s built-in modules covering a range of topics such as analog IP design, RISC-V SoC design, PCB design, and more, learners can acquire practical skills and knowledge essential for a career in the field. In summary, the VSDSquadron educational board offers a rich and dynamic learning experience in electronics system design and chip design.
International payments are now open. You can pre-order your board using below link
1. What is a latch? Explain using NOT, NAND, and NOR gates.A latch is a type of digital circuit that is used to store and […]
If you have been following VSDOpen for the last 5-years, the theme has been maintained – What VSD did last year and what VSD will do next year
VSDOpen conference is an attempt to bring out some cutting-edge activities especially around open-source EDA with a special focus on skill development using open and proprietary tools. VSDOpen also focuses on milestones achieved by VSD in the past year, and some interesting projects which VSD will be working on in the next year. It’s like the VSD Annual Hands-on meeting where everyone is invited for free and allowed to rate us for our work 🙂
VSD – IIIT Bangalore – Unique example of industry-academia collaboration – 12 chip tapeouts in 2 months
VSD-IIIT Bangalore to set a unique industry-academia model for all colleges across India regarding how tapeout-oriented ASIC design courses can be a part of a full semester curriculum, given the amount of flexibility for curriculum change and mapping to latest industry needs. And thanks to Google/Skywater/efabless for opening up the foundry information, due to which we were able to provide chip design and manufacturing experience to a whole cohort.
Traditional pieces of training have taken an orthogonal shift, post-release of open-source EDA tools and SKY130 foundry. This has brought a huge opportunity for semiconductor ed-tech companies like VSD to close a wide gap within many training companies that have shifted their curriculum from theoretical PDK to real PDK. If you are a student, who is reading this email, do not panic if you are not aware of PDK. This is something which we are covering in the workshop.
Join us to explore such concepts and more, where we use Python to leverage its library-rich environment feasible for verification using Vyoma’s UpTickPro platform, in this edition of Capture the Bug hackathon, organized by NIELIT, Calicut, mentored by IIT Madras, in association with VLSI System Design and Vyoma Systems.
Hackathon details – https://nielithackathon.in/
In a nutshell, the project really is to build a Verilator Verification environment i.e. a structure in which we can set up testbenches that are executed with Verilator. The thing which is interesting in this project is we are going to tie that Verilator piece with a golden model arithmetic library and that is going to be something that you can publish as nobody else in the world has that
It’s a Verilator Testbench environment that uses an online arithmetic library to generate the right bit pattern. We are not using randoms, but we are using a Golden model. If you progress from ALU to a vector accelerator, you will have a vector lane, vector register file, vector load/store unit, vector instructions.