The different projects which we have here are 1) modifying RISC-V core so that it recognizes all these instructions to a vector accelerator 2) vector accelerator itself is decoding vector instructions and managing the execution and retirement of these vector instructions
In a nutshell, the project really is to build a Verilator Verification environment i.e. a structure in which we can set up testbenches that are executed with Verilator. The thing which is interesting in this project is we are going to tie that Verilator piece with a golden model arithmetic library and that is going to be something that you can publish as nobody else in the world has that
It’s a Verilator Testbench environment that uses an online arithmetic library to generate the right bit pattern. We are not using randoms, but we are using a Golden model. If you progress from ALU to a vector accelerator, you will have a vector lane, vector register file, vector load/store unit, vector instructions.
You might have seen the above image in one form or another, in different our blogs or VSD websites. Every trapezoid in above image is […]
Mohammad joined VSD as a part of 8-week Hardware Design Program (HDP), which is specially designed for anyone looking to reach utmost level of VLSI from scratch.
VSD promises to deliver similar IP design workshops in upcoming days, followed by the next big leap – SoC design workshop with VSD SoC generator using all VSD IPs developed by VSD community using Skywater 130 nm technology node.
“What I did in the 5-day Advanced Physical Design workshop?” – Experiencing the “freedom within expanding boundaries”
I have been tracking opensource tools in backend flow and also VSD’s online programs like MYTH, Digital System Design, Modelling using Verilog etc. In the […]
In this 8-week internship I spent the first week on researching existing work and making design decisions for the PLL components namely – Phase Frequency Detector, Charge Pump, Voltage Controlled Oscillator and Frequency Divider. I also looked into linking of the Sky130nm PDK with SPICE for the circuit implementation.
RISC-V and open-source hardware is undoubtedly destined to change the industry. Not just for the ISA and design, there are ongoing efforts to tape out an actual chip with completely open-source tools!
Join the revolution!
A few months back, I came across a workshop titled ‘RISC-V based Microprocessor for You in Thirty Hours (MYTH)’, that was about designing RISC-V core […]
Power analysis has materialized as a principal theme in today’s world in semiconductor industries. As very large scale integrated circuit (VLSI) are far beyond from human ability because of complexity in nature. So to analyse power in these circuits we use open source computer aided tools, plenty of tools are available but most of them are costly. I designed an open source power analysis tool for the academic use. This tool gives out values of average and leakage power of any circuit by just giving the netlist of circuit file along with name of supply voltage as input. This tool is designed in python language.