150+ students have decided to upskill in VLSI

And that’s where VSD must play an especially important role to bring in latest and greatest VLSI skills to you, atleast in the field of open-source hardware. VSD owes a lot to VLSI community and hence has planned 3 exclusive cloud lab-based VLSI workshops on 3 important topics, with top 3 expert instructors from around globe,  having more than 2 decades of experience – Tim Edwards, Steve Hoover, and Prof. Mohamed Shalan

Open-source EDA tool development with lab exercises using Sky130 pdk’s by Google/Skywater
RISC-V micro-architecture using transaction level – Verilog with lab exercises on Makerchip Platform
SoC and Physical Design using Automated RTL2GDS OpenLANE tool with lab exercises using demo design and Sky130 pdk’s.

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7th mile-stone in open-source analog IP design – 10-bit DAC

Ashutosh had joined our VSD Research IP design internship group 8-weeks back, along with 30 other interns. His journey on was from “I can’t, its too difficult” to “I did it”. Personally, only I know how hard it was for him when he saw an industry grade 10-bit DAC specifications on VSD IP website. We managed to achieve post-layout DNL of 3.5LSB and INL of 3.7LSB, which as per experience, is really tough for a fresher to achieve in a span of 8-weeks, but not impossible.

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2nd mile-stone in field open-source (open-lane EDA + Google/Sky130)

@Nickson joined our research project group under VSD Research internship program which runs for 8-weeks. He was supposed to develop flow for standard cell design and characterization using all open-source tools – magic/ngspice, then plug those standard cells into open-source PNR flow by open-lane, and benchmark RTL2GDS flow results. This needed a knowledge, not only of PNR, but device physics, custom layout, DRC/LVS and then (finally) Physical design/STA.

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Keynote 1(Continued): Inception of Intel 8086

It wasn’t that bigger deal for Intel because they thought, at the time, it will be 250,000 chips will be sold for 5 years, which isn’t that many. But they were wrong. It was a 100Million computers were sold. And suddenly 8086 from being an emergency back-up was an over-night success and had a very bright future, because it was binary compatible of PC software, and so had great opportunity

Isn’t that an inspiring story?

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A new golden age for computer architecture by Prof. David Patterson

In last 50 years, there are 3 lessons that we can draw. First – software advances can inspire architecture innovations. Second – when we raise the hardware/software interface, it creates opportunities for architecture innovation. Third – in our field, the way we settle these debates, isn’t by just arguing in a bar, rather people spent/invest billions of dollars to investigate their ideas and marketplace settles these debates

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Paper 6: Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator

This paper introduces TL-V erilog and W ARP-V and then describes the formal verification of WARP-V using riscv-formal, a formal verification framework for RISC-V. Timing-abstraction and transaction-level design are showing significant benefits for hardware modeling, but this is the first demonstration of their benefits for verification modeling. As evidence of these benefits, the verification of all RISC-V configurations of WARP-V is accomplished in a single page of code.

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Paper 5: Introduction to TL-Ver & Front-End Symposium

Steve Hoover is the founder of Redwood EDA. Steve holds a BS in electrical engineering from Rensselaer Polytechnic Institute and an MS in computer science from the University of Illinois. He has designed numerous components for high-performance server CPUs and network architectures for DEC, Compaq, and Intel. Students will learn Transaction-Level Verilog modelingtechniques to generate Verilog models in half the time using the makerchip.comfree online IDE. A new open-source RISC-V CPU development effort will be introduced that showcases flexible IP design practices.

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Paper 3: Coverage Driven Functional Verification on RISC-V Cores

Design Verification is critical to proving functional correct- ness and establishing confidence in a design. Several stud- ies from industry and academia, particularly over the course of the last two decades, have explored various verifica- tion methodologies that fall somewhere between dynamic or purely static formal approaches.
System-on-Chips (SoCs) today have become extremely complex structures housing heavily optimized cores, count- less peripherals, and large interconnect fabrics. Even re- stricting ourselves to just verifying the microprocessor, the state space to be verified is enormous and cannot be exhaus- tively explored in any finite amount of time. Manually writ- ten tests, while effective at capturing some complexities of design intent, suffer from the fact that they are expensive in cost and time required to develop them. Random stimulus methods perform better because they eventually cover many cases. Most new ideas in dynamic verification over the last two decades have largely been towards semi formal verifi- cation methodologies such as coverage driven verification and constrained test generation. In this paper, we explore an approach to dynamic functional verification that we use at the RISE lab, IIT Madras for the verification of the RISC-V based Shakti cores.

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