1. What is a latch? Explain using NOT, NAND, and NOR gates.A latch is a type of digital circuit that is used to store and […]
If you have been following VSDOpen for the last 5-years, the theme has been maintained – What VSD did last year and what VSD will do next year
VSDOpen conference is an attempt to bring out some cutting-edge activities especially around open-source EDA with a special focus on skill development using open and proprietary tools. VSDOpen also focuses on milestones achieved by VSD in the past year, and some interesting projects which VSD will be working on in the next year. It’s like the VSD Annual Hands-on meeting where everyone is invited for free and allowed to rate us for our work 🙂
VSD – IIIT Bangalore – Unique example of industry-academia collaboration – 12 chip tapeouts in 2 months
VSD-IIIT Bangalore to set a unique industry-academia model for all colleges across India regarding how tapeout-oriented ASIC design courses can be a part of a full semester curriculum, given the amount of flexibility for curriculum change and mapping to latest industry needs. And thanks to Google/Skywater/efabless for opening up the foundry information, due to which we were able to provide chip design and manufacturing experience to a whole cohort.
Traditional pieces of training have taken an orthogonal shift, post-release of open-source EDA tools and SKY130 foundry. This has brought a huge opportunity for semiconductor ed-tech companies like VSD to close a wide gap within many training companies that have shifted their curriculum from theoretical PDK to real PDK. If you are a student, who is reading this email, do not panic if you are not aware of PDK. This is something which we are covering in the workshop.
Join us to explore such concepts and more, where we use Python to leverage its library-rich environment feasible for verification using Vyoma’s UpTickPro platform, in this edition of Capture the Bug hackathon, organized by NIELIT, Calicut, mentored by IIT Madras, in association with VLSI System Design and Vyoma Systems.
Hackathon details – https://nielithackathon.in/
For the upcoming Capture The Bug Hackathon, participant is free to choose any Verilog Open Source design from any website/reference similar to that of OpenCores with appropriate licensing which is compatible with Icarus Verilog and also the Verilog code needs to be synthesizable.
The working of digital computers, smartphones, etc all have some underlying basic logic manipulating just 0s and 1s to come up with interesting outcomes. With […]
The different projects which we have here are 1) modifying RISC-V core so that it recognizes all these instructions to a vector accelerator 2) vector accelerator itself is decoding vector instructions and managing the execution and retirement of these vector instructions
You might have seen the above image in one form or another, in different our blogs or VSD websites. Every trapezoid in above image is […]