Open Source – VLSI System Design

VSD – IIIT Bangalore – Unique example of industry-academia collaboration – 12 chip tapeouts in 2 months

VSD-IIIT Bangalore to set a unique industry-academia model for all colleges across India regarding how tapeout-oriented ASIC design courses can be a part of a full semester curriculum, given the amount of flexibility for curriculum change and mapping to latest industry needs. And thanks to Google/Skywater/efabless for opening up the foundry information, due to which we were able to provide chip design and manufacturing experience to a whole cohort.

Why is a Physical Design workshop important for education?

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Hi Kunal

Traditional pieces of training have taken an orthogonal shift, post-release of open-source EDA tools and SKY130 foundry. This has brought a huge opportunity for semiconductor ed-tech companies like VSD to close a wide gap within many training companies that have shifted their curriculum from theoretical PDK to real PDK. If you are a student, who is reading this email, do not panic if you are not aware of PDK. This is something which we are covering in the workshop.

Random Verification in Hardware – A Primer

Join us to explore such concepts and more, where we use Python to leverage its library-rich environment feasible for verification using Vyoma’s UpTickPro platform, in this edition of Capture the Bug hackathon, organized by NIELIT, Calicut, mentored by IIT Madras, in association with VLSI System Design and Vyoma Systems.
Hackathon details – https://nielithackathon.in/

Opencores.org – Encyclopedia to begin the Hackathon

For the upcoming Capture The Bug Hackathon, participant is free to choose any Verilog Open Source design from any website/reference similar to that of OpenCores with appropriate licensing which is compatible with Icarus Verilog and also the Verilog code needs to be synthesizable.

Happy Verification!!!

Design Verification hackathon means what?

The working of digital computers, smartphones, etc all have some underlying basic logic manipulating just 0s and 1s to come up with interesting outcomes. With […]

VSD-HDP on Tensor Core – A RISC-V Vector Accelerator for deep learning applications

The different projects which we have here are 1) modifying RISC-V core so that it recognizes all these instructions to a vector accelerator 2) vector accelerator itself is decoding vector instructions and managing the execution and retirement of these vector instructions

Skywater130 Spec to GDS workshop details

You might have seen the above image in one form or another, in different our blogs or VSD websites. Every trapezoid in above image is […]

What I did in 8-weeks-VSD Internship? – Vezzal

Constant development of tools often breaks something internally which can lead to other issues. Hence there is a need to test the tool for its previous supporting features. But the tool needs an environment to get launched and good test cases to test the features. This is called as “Continuous Integration (CI)”. I

Chip Tape-out – Not a dream anymore – VSD students prove it again

From nothing to Tapeout Ready basic designs – These 7 students have seen it all. Congratulations to all of them. Great start to their semiconductor career.
Here’s the link with their design details-

VSD delivered 1st online analog tapeout workshop using Sky130

VSD promises to deliver similar IP design workshops in upcoming days, followed by the next big leap – SoC design workshop with VSD SoC generator using all VSD IPs developed by VSD community using Skywater 130 nm technology node.