VSD is enabling VLSI engineer to develop this versatile skills of designing and development using all the open source resource with in-depth research skill. VSD is working on the research based economical training modules where engineers are taught to learn knowledge from the industry leaders, we provide cloud lab based platform where they can understand the design concepts and finally with our hardware design program engineer apply the design skills to develop silicon ready IPs and design etc.

VSD has been conducting Hardware design programs for 3 years now and seen some amazing results, like great opensource IPs, amazing solutions for power analysis, innovations using Sky130 PDKs and close to 50+ silicon ready designs awaiting tape-outs. The reason for the success of HDP is the level of freedom which it allows for innovation.

VSD follows a strict 5-stage process, which is a typical practice in top semi-conductor design companies, thereby, providing an experience which is similar work working for a design company.  That is the reason this program is recommended by some top industry professionals who are the recruitment head.

Potential Project / Technologies for Upcoming HDP:

Here is a list of probable projects on which you will be working on for 10-weeks.

Project Title



10 bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

{Project code : DAC}

The project aims to design a 10-bit Potentiometric Digital to Analog Converter using end-to-end Open-source EDA tools. The target is to design 10-bit potentiometric DAC with 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference using sky130nm technology node.

High Frequency analog VCO design and implementation using Sky130

{Project code : KCEDVCO}

200MHz, 400MHz and 915MHz VCO design using Sky130nm - from specification to tapeout

Low Dropout Regulation :A low-dropout regulator (LDO) is a DC linear voltage regulator that can regulate the output 
voltage that is powered from a higher voltage input. 

{Project Code:LDO}

LDO  Specifications:
1.     Technology: Google Sky water 130nm 
2.     Input power supply range: 2-to-5 V
3.     Output Voltage: 1.8 V
4.     Load current: 10 mA
5.     Temp range: -40 to 125 Degree cent.
6.     Circuit current: 0.5 mA
7.     Reference Voltage: 1.2 V @ < 50 ppm

NEW - Circuit Design for Capacitive Sensing - Touch/Pressure

{Project code -  CDCST}

The capacitance to digital converter (CDC) are being extensively used in Biomedical diagnostics, Water and level sensing applications in Industrial sector, MEMS sensor interface and plenty of hobby projects by young engineers. The basics of capacitance sensors, types of cap sensors - Floating and Grounded and their construction is discussed. Learn about the interdigitated Capacitor platform for many Gas Sensing applications and pressure sensing applications. 

Physical Design and Static Timing Analysis 

rvmyth integration with PLL, DAC and SRAM using Sky130

{Project code - RPDS}

RISC-V based SoC design, implementation and tapeout using VSD Sky130 IPs

Performance characterization for VSDBabySoC comprising of RISC-V core, PLL and DAC

{Project code - PCVRPD}

Analyze and characterize RISC-V based VSDBabySoC for all timing corners, fix timing violations, ECO, implement and tapeout

rvmyth : RTL2GDS with OpenLane with the standard cells from Libresilicon StdCellLib generated standard cells for SKY130   

{Project Code:ROLS}

Take the LibreSilicon Standard Cells for the SKY130 process (https://pdk.libresilicon.com/dist/StdCellLib_20210618/Catalog/buildreport.html) and synthesize a RVMYTH design using those standard cells with OpenLane, preferably directly into an EFabless Caravel User-Space.

Parallel Static Timing Analysis

{Project Code:PSTA}

In this project, we will build a parallel STA algorithm on top of the open-source software, OpenTimer. We will start with understanding the runtime bottleneck of OpenTimer on a large industrial design of millions of gates. Then, we will dive into the core algorithm of OpenTimer and learn how to parallelize it using manycore CPU parallelism. Finally, we will demonstrate the speed-up compared to the original version.


1st CLaaS for Local FPGAs

{Project code - 1CLF}

1st Class supports web application communication with FPGA logic in the cloud. Support local FPGA use cases as well. This is useful for local applications as well as to support development that will ultimately be deployed to the cloud.

World CLaaS: Open FPGA Cloud

{Project code - WCOFC}

The vision is to enable individuals with FPGAs (World CLaaS Citizens) to share their hardware with the world

WARP-V Many-core Accelerator Microservice

{Project Code - WMAM}

It will provide a configurable, easily-modifiable many-core-on-FPGA hardware accelerator deployed as a microservice to accelerate web and cloud applications.



{Project code - TVTCTC}

TL-Verilog is a Verilog implementation of TL-X, and currently Verilog is the only target language for TL-X. This project would see through the vision of layering transaction-level support on other languages. TL-VHDL would help to broaden the reach of the technology. TL-C would connect transaction-level design with System-C and therefore high-level synthesis. And, TL-Clash would explore the integration of transaction-level modeling with a stronger type system among other language benefits.

Fractal Valley

{Project code - FV}

This project turns the demo into a robust site showcasing the value of hardware-acceleration in the cloud and the fun world of fractals.

ONFI compliant NAND Flash controller on Sky130 

{Project Code:ONFI}

An ONFI-compliant NAND Flash Controller in Verilog 2005 or TL-Verilog. License: It needs to be licensed under an Opensource license, e.g. Apache 2.0. The resulting Verilog code needs to be made available on a GitHub repository

New- Enabling SDC switches in Yosys

{Project Code:ESSY}

Yosys is an open source logic synthesis tool . Unfortunately there is no support for the regular SDC in Yosys. The aim of the project is to take certain specific constraints in SDC
like set_max_delay , set_input_delay , set_input_transition , etc and enable the equivalent features in Yosys by creating custom synthesis scripts. The scope of this project gives a very good exposure to
Verilog coding skills, Working of synthesizer, Logic optimization knobs in logic synthesis, Design constraints


Verification of Vector machines for Deep Learning

{Project Code: VVMDL}

Verification of Vector Machines for Deep Learning: to drive adoption of open-source hardware solutions, high-quality and demonstrable verified designs are essential. This project is building a reusable verification infrastructure and regression workflow using modern open-source tools.


{Project code - TLUVM }

In theory, TL-X should be applicable to UVM as well. Since UVM does not have open-source support, no one has yet tried. But it would be great to uncover issues and put together examples. It looks like Modelsim supports UVM and is freely available for Intel FPGAs. There might be other options.


Visualization of SweRV

{Project code - VOS}

The SweRV core is an open-source SystemVerilog RISC-V CPU core developed by Western Digital. It is an interesting core for college course and is being highlighted in the RVfpga course for one. Visualizing the operation of the core can greatly enhance the learning experience. This project aims to do so. SweRV is be built and simulated within Makerchip

Implementing other ISAs in WARP-V

{Project Code - IIW}

WARP-V currently has support for RISC-V, (incomplete) MIPS, and a toy educational ISA. PowerPC is also open now and could be implemented, in addition to any other open ISAs.

Neural Net

{Project code - NN}

We have created a simple configurable neural network model in TL-Verilog. This could follow a similar path to WARP-V w/ a configurator and cloud FPGA implementation. The WARP-V configurator is build in a modular fashion to support this easily.

TensorCore Accelerator for Machine Learning

{Project code - TCAML}

This project focuses on implementing a Deep Learning hardware accelerator called TensorCore - which is a Vector Processor based on v0.10 of the open source RISCV Vector ISA. It is expected to serve as a proof-point for a Deep Learning research platform to experiment with tensor operators and custom number systems


Visualization of the TLV Flow Library

{Project Code - VTFL}

This project adds visualization to components in the TL-Verilog FLow Library. It explores encapsulation of visualization and aspect-oriented visualization that decouples transaction visualization from component visualization.

Visualization for BaseJump STL

{Project Code - VBJS}

BaseJump STL is a library of SystemVerilog components used in the design of Black Parrot. This might be a good candidate for use of VIZ, both for Black Parrot and to augment BaseJump STL with generic visualization. This would explore the use of generic visualization of SystemVerilog components.

Visualization for basic digital logic instruction

{Project Code - VBDLI}

VIZ can be used to illustrate basic logic functions and concepts like logic gates, K-maps, pipelines, etc. This project would develop these visualizations. Bala Dhinesh implemented [basic logic gates]

TL-Verilog Editor Modes

{Project code - TVEM}

This general category of smaller projects improves the ecosystem for TL-Veriog development by creating editor support for various text editors and IDEs. Many editor modes already exist. A few possibilities include:
- Adding JavaScript editing support within the TL-Verilog mode for Code Mirror (used by Makerchip) for `viz` blocks
- Improved support for M4 editing in TL-Verilog mode for Code Mirror.
- GitHub support for TL-Verilog

EDA Microservices

{Project code - EDAM}

Makerchip currently supports simulation of Verilog and TL-Verilog code. It is expanding to support logic synthesis and other physical flows as well as support for other HDLs. This project will provide various microservices that run open-source eda tools that can be incorporated into Makerchip.

TL-Verilog Timing Reports

{Project code - TVTR}

This project will help designers to relate timing information from synthesis tools back to TL-Verilog's higher-level context (hierarchy, pipelines, and transactions). Scripts are needed to map RTL signal names to their original TL-Verilog names. This will be applied to timing reports from open source synthesis tools so timing information can be reported with respect to TL-Verilog source code.

DRC Test Generator 

{Project Code:DRCTG}

The goal is to develop a tool that takes DRC rules as an input in the MAGIC tech file format, and to generate for each of the rules at least 2 (or more if that makes sense for the specific rule) test-structure test-cases, a good test case (where the test-structure fulfills all DRC rules), and a bad test case (where the test-structure fulfills all other DRC rules but it breaks the given rule). Where it is useful, please add edge cases that could be discussed, or add rotated cases to check horizontal/vertical.

Reproducible Builds for OpenLane/TheOpenRoad 

{Project Code:RBFO}

Test for reproducibility, file any reproducibility issues with the respective project/subproject and Philipp Gühring, work on solutions

DRC Correction Engine: Analyze common DRC issues, automatically detect and solve them, integrate the DRC fixing functionality into Magic.     

{Project Code:DRCE}

Expand magic so that “drc why” can explain all potential layers for a given DRC failure without the annotated design rules

Liberty File HTML Report generation with tables and diagrams (Input: .LIB Output: HTML Report), compare 2 different liberty files, report similarities and differences.  

{Project Code:LFHR}

Develop a tool which takes a liberty file and generates a report about all the contents found in the file, it should display the tables and provide visualization (diagrams/graphs/3D) the values where possible. Display meaningful aggregation data like Minimum/Maximum values for tables. The second part is to enhance the tool to be able to compare 2 different liberty files. This should help the user to answer the following questions: Which parts of the files are equal? Which parts of the file are different? (e.g. are the power models missing in one of the files?) Are the same basic units used? (e.g. Micrometers vs. Nanometers)? Are the same Timing models used? (NLDM/CCS/ELDM/none)? Are the two liberty files possibly covering the same cell? (Do they have the same number of inputs and outputs?) How far off are the timing numbers? (E.g. Identical, within 1%, within 5%, within 10%) It would be great if this check would even be done in case of different timing models (e.g. NLDM/CCS/..) or when the whole file is using different basic units, or even when the timing models are covering slightly different data points.


Program Date : 12 August 2022

Fees : $999

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