VSD-Hardware Design Program

With VSD Hardware Design Program (VSD-HDP),  you have the opportunity to push the boundaries of what exist in open source and establish the new benchmark for tomorrow. It will leverage your degree in Electrical or Computer Engineering to work with programmable logic, analog/ digital IP, RISC-v, architecture, microprocessors, ASICs and SoCs on high-density digital or RF circuit cards and gain hands-on knowledge during design validation and system integration.

Sounds exciting to just get started with expert mentors, doesn’t it? But we are looking for the next generation of learners, inventors, rebels, risk takers, and pioneers.

“Spend your summer working in the future !!”

Program Benefits

Github Resume

Webinar with VSD after 100 % completion

Tapeout Opportunity*

Open Source Mentor

Tim Edwards

Kunal Ghosh

Steve Hoover

Philipp Gühring

Program Duration: 17 July – 11 September 2021

Registration Fees: $999 or INR 72,000/-

Indian Student

International Student

Potential Project / Technologies:

VSD-Hardware Design Program

Sr.noProject NameProject code
3SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns (OpenRAM)SRAM
410 bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage referenceADC
5OpenRoad RTL2GDS for mixed signal SoC (Inputs = mixed signal Verilog, openroad RTL2GDS tools, outputs = GDSII)RTL2GDS
6Bi-directional Buffer with Non-Inverting CMOS Input and Gated Pull-down and Pull-up, Strength 4mA @ 3.3V, Normal, High noise (Fast speed)BIDIBUFF
710bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage referenceDAC
8On-chip Clock multiplier (pll) (Fclkin – 5MHz to 12Mhz, Fclkout – 40MHz to 100MHz at 1.8vPLL
9Lower power current programmable CMOS comparator with hysteresisCOMP
10Open-source Layout Generator (Inputs = Digital or Analog Circuit, Output = Layout) (Ref:OpenRAM, LCLAYOUT)LAYOUT
11PadCell PadPAD
12PadCell RouterROUTER
13PadCell ESDESD
14PadCell Power Lanes + Pad CellLANES
15PadCell Corner CellsCORNER
16PadCell Guard RingsGUARD
17PadCell InterfaceIFCORE
18PadCell Putting it all togetherPADCELL
19PadCell testingPADTEST
20PadCell characterizationPADCHAR
21PadCell RTL2GDS flow supportPADFLOW
23RTL2GDS with OpenLane with the standard cells from Libresilicon StdCellLib generated standard cells for for LibreSilicon 1um Process NodeLSQFLOW
24RTL2GDS with OpenLane with the standard cells from Libresilicon StdCellLib generated standard cells for SKY130SKYQFLOW
25Reproducible Builds for OpenLane: Trying to reproducibly build a chip with qflow. Document all problems. Research reasons and possible countermeasures. Develop fixesREPRODQFLOW
26Reproducible Builds for TheOpenRoadProject/TheOpenLaneREPRODROAD
27Process Node MapPROCESSMAP
28Research: Search for all+exotic standard cellsEXOTICCELL
29C++: Parametric support for hierarchical sheets in EESchema, GUI+ Fileformat, for V6KICADPARAM
30Recognize the function of a cell based on the netlist or the truth tableFUNCTIONID
31DRC Test Generator for Good and Bad ExamplesDRCEXAMPLE
32LibreCell layout live preview (like graywolf)LCLAYOUTLIVE
33DRC Correction Engine: Analyze common DRC issues and try to write a tool that automatically detects them and solves them (while not making things worse 🙂DRCCORRECT
34Popcorn growingPOPCORN
35Improve Popcorn to grow cells automatically (without predefined their relationships in Makefiles)POPCORNAUTO
36Yosys Synthesis Segmentation for huge designsSEGMENTATION
37Datascience: LCLayout + LCTime Meta-ParametersMETAPARAM
38Create a a tool that calculate number of stages from a Spice NetlistCALCSTAGES
39Liberty File HTML Report generationLIBERTYHTML
40Liberty File Comparison: Compare 2 different liberty files, report similarities and differencesLIBERTYDIFF
41Generate a standard cell library for Path Programmable Logic / Asynchronous LogicASYNC
42Synthesize a chip with Path Programmable Logic in qflowASYNCQFLOW
45WARP-V (RV32IMF) SoC design with existing analog IP’sRISCVSOC
46RTL2GDS with OpenLane with the standard cells from StdCellLib for Libresilicon 1umLSLANE
47RTL2GDS with OpenLane with the standard cells from StdCellLib for SKY130SKYLANE
48OpenFPGA design for SKY130OPENFPGA
50Reproducible Builds for StdCellLib: Trying to reproducibly build a standard cell library.REPRODCELL

Outcomes of VSD Online Research IP Design Internship Program

  1. Job opportunities in Semiconductor Industry
  2. Research work can be submitted to VLSI International journals
  3. Participate in Semiconductor International Conference with Internship Research Work
  4. Paper Publications in IEEE Conference and SIG groups
  5. Tape out opportunity and IP Royalty
  6. Interact with world class Semiconductor designer and researchers
  7. Academic professions where more research projects are encouraged.
  8. All the above research and publication work will help colleges and institutes to improve accreditation levels.