The course introduces ASIC design flow, which is an iterative process but not static for every design. The base concepts remain the same, however, the details of the flow, like ECOs, IP requirements, DFT insertion, and SDC constraints, may change.

Below are the fundamental steps for ASIC design flow, which will be covered during the duration of the course:

1. Architectural Design – A system engineer will provide the VLSI engineer with specifications for the system that are determined through physical constraints. The VLSI engineer will be required to design a circuit that meets these constraints at a microarchitecture modelling level.
2. RTL Design/Behavioral Modeling – RTL design and behavioral modelling are performed with a hardware description language (HDL). EDA tools will use the HDL to perform mapping of higher-level components to the transistor level needed for physical implementation. HDL modelling is normally performed using either Verilog or VHDL. One of two design methods may be employed while creating the HDL of a microarchitecture
3. RTL Verification – Behavioral verification of design
4. Logic Synthesis – Logic synthesis uses the RTL netlist to perform HDL technology mapping.
5. Post-Synthesis STA Analysis – Performs setup analysis on different path groups.
6. Floorplanning – The goal is to plan the silicon area and create a robust power distribution network (PDN) to power each of the individual components of the synthesized netlist. In addition, macro placement and blockages must be defined before placement occurs to ensure a legalized GDS file. In power planning, we create the ring which is connected to the pads and brings power around the edges of the chip. We also include power straps to bring power to the middle of the chip using higher metal layers which reduces IR drop and electro-migration problems.
7. Placement – Place the standard cells on the floorplan rows, aligned with sites defined in the technology LEF file. Placement is done in two steps: Global and Detailed. Global placement tries to find the optimal position for all cells, but they may be overlapping and not aligned to rows, detailed placement takes the global placement and legalizes all the placements trying to adhere to what the global placement wants.
8. CTS – Clock tree synthesis is used to create the clock distribution network that is used to deliver the clock to all sequential elements. The main goal is to create a network with minimal skew across the chip. H-trees are a common network topology that is used to achieve this goal.
9. Routing – Implements the interconnect system between standard cells using the remaining available metal layers after CTS and PDN generation. The routing is performed on routing grids to ensure minimal DRC errors.

We will use the OpenLANE RTL2GDS open-source EDA tool. OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, SPEF-Extractor and custom methodology scripts for design exploration and optimization. It is a tool started for true open-source tape-out experience and comes with APACHE version 2.0. The goal of OpenLANE is to produce clean GDSII without any human intervention. OpenLANE is tuned for Skywater 130nm open-source PDK and can be used to produce hard macros and chips.

Why is it important?

VLSI integrated circuits have revolutionized the industrial world. They are ubiquitous and are being deployed in every conceivable engineering system – from the simplest to the most complex. It is imperative to have the right skill sets amongst our graduating students to render these extremely complex chips efficiently and with a minimum number of re-spins as the Silicon processing steps to realize them have a very high cost.

The reason for using open-source EDA tools is to enable students to collaborate freely across organizations even after the course is over as there are no legal agreements to use open-source technology. With the advent of SKY130 PDKs, it enables easy access to tape-out shuttles which are currently sponsored by Google.

Below is the list of projects which a participant can choose during the HDP program.