The horrible std cell ever designed by me….

Power rail discontinuity – We would like to have continuous power rail.N- and P-diffusion discontinuity – We would like to have continuous diffusion. For my Physical design friends, remember, we add “FILLER” cells at the end of routing, and you always wondered why we are doing so.Small substrate contacts – Except for inverter, all substrate contacts are single width, which will create high resistance path for current, thus increasing “Clk-to-Q” delay.Hanging metal1 – If you see for the NAND gate outputs, there is lot of hanging metal1.

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Are you ready for Embedded-UVM webinar?

Hey There, Of-course there is a requirement for open-source verification, but that’s not the only thing we want to cater to. There are other verification trends and challenges which system verilog and other verification platforms are not able to meet. So, we want to position Embedded-UVM for that In the […]

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I wanna talk to hardware…I need Embedded Software Engineer

Hey There, It’s time – We are looking to talk to our hardware, and we need you in Bangalore (2-3 or 4-6 yrs work ex) Read below very carefully, and if you think you fit, please send us email at “contactvsd@vlsisystemdesign.com”…. If you have experience Developing/Reviewing/Verification and testing maintainable, high […]

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How about pre-route and power-grid generation in opensource EDA?

Hey There – Think about it!! Today’s version of open-source EDA tools, work very well for hierarchical designs sub-25k instance count. For hierarchical designs ~500k instance count, develop code which will enable users to connect pre-placed power pins to power rings around them and generate power grid within core Inputs […]

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Now that’s the beauty of open-source….

Hey There, Our team worked really hard to get Robot + MP3 player using India’s First Indegenious 32-bit RISC-V Microprocessor “Shakti E-Class”…This one is Shakti on FPGA….Many more customer products are getting ready using Shakti processor and indigenous board, for IESA event at Leela Palace, Bangalore on 19th and 20th […]

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Re-define pad placement using open-source EDA

Hey There – Think about it!!! Last week, we shared our idea and vision of “How to define the width and height of core and die using opensource EDA tools?” – This is not for toy designs, but for a complex hierarchical designs, with instance count up to 500k instance […]

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Let’s re-think open-source EDA – core and die

Hey There – Think about it!!! Today’s version of open-source EDA tools, work very well for hierarchical designs sub-25k instance count. For hierarchical designs ~500k instance count, what if, we develop code which will enable users to design/decide chip area based on width and height of chip OR utilization factor […]

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