VSDSquadron
RISC-V and VLSI Educational Board
One Chip One Board One Lab Setup with Open Tool Chain
Overview
Furthermore, the RISC-V chips on these boards should be open for VLSI chip design learning, allowing you to explore PNR, standard cells, and layout design. And guess what? VSDSquadron is the perfect solution for all your needs! With its comprehensive documentation and scalable labs, thousands of students can learn and grow together. The VSDSquadron is an educational kit with general-purpose interfaces that enables you to evaluate features of RISC-V ISA.
What is VSDSquadron?
Development Board
An educational kit and cutting-edge development board. With general-purpose interfaces that enables to evaluate features of RISC-V ISA
Opportunity
An exceptional opportunity for individuals to learn about RISC-V and VLSI chip design utilizing only open-source tools.
Gateway to RISC-V Programming
VSDSquadron labs are designed to get started with RISC-V programming, synthesis, physical design, and circuit design.
Industry-Grade Educational Content
Kit includes RISC-V Programming and VLSI Chip Design industry grade educational content.
Build Application
The VSDSquadron board comes with a minimum of 10 GPIOs, which makes it ideal for a diverse range of projects.
Kit Modules
VSDSquadron Modules covers RISC-V Basics, RTL Design and Synthesis, Physical Design, Circuit design and SPICE simulations.
Kit Includes
Gain lifetime access to comprehensive RISC-V Programming and VLSI Chip Design educational content with the release of the new VSDSquadron board, featuring over 10 GPIOs for diverse projects. This package includes extensive labs and theory modules covering RISC-V ISA, GNU compiler toolchain, integer arithmetic, circuit design, and SPICE simulations, aimed at enhancing skills from basics to advanced levels. Pre-order to be among the first to dive into this rich learning experience and elevate your RISC-V programming and chip design capabilities.
Board Features
Labs Overview
Theory Modules
Curriculum
- VLSI Ed-Tech Introduction
- Introduction to RISC-V ISA and GNU compiler toolchain
- Introduction to ABI and basic verification flow
- Need for IP design
- IP design Prerequsite - Basics of NMOS Drain current (Id) vs Drain-to-source Voltage (Vds)
- IP design Prerequsite - Velocity saturation and basics of CMOS inverter VTC
- IP design Prerequsite - CMOS Switching threshold and dynamic simulations
- IP design Prerequsite - CMOS Noise Margin robustness evaluation
- IP design Prerequsite - CMOS power supply and device variation robustness evaluation
- Analog IP design example
- Introduction to Macros
- Introduction to Verilog RTL design and Synthesis
- Timing libs, hierarchical vs flat synthesis and efficient flop coding styles
- Combinational and sequential optmizations
- GLS, blocking vs non-blocking and Synthesis-Simulation mismatch
- Inception of open-source EDA, OpenLANE and Sky130 PDK
- Good floorplan vs bad floorplan and introduction to library cells
- Design library cell using Magic Layout and ngspice characterization
- Pre-layout timing analysis and importance of good clock tree
- Final steps for RTL2GDS using tritonRoute and openSTA
- Mixed Signal SoC Design and Full Chip RTL2GDS
- Project Work - Chip Testing planning
- Project Work -Using “VSDSqaudron” development of RISC-V application
Projects
Semicon India Aug 2023 Gujarat
7 Segment LED Counter
Line Follower Robot
Home Automation
Pan India RISCV Roadshow on VSDSquadron
About VSD
Online Beginner Course
RTL GDSII VSD-IAT Workshop
VSD Community Based Silicon Tape Out
Analog & Mixed Signal IPs
VSDOpen Online Conference
Unique Global students
VSD Hackathon Participants
VSDSquadron Educational and Dev Kit
Over the past decade, VSD has made remarkable strides in the open-source semiconductor domain. Our journey includes the development of comprehensive training content, empowering students to design silicon-grade IP/SoC. Notably, we’ve successfully guided these projects through the tapeout cycle via the Google open shuttle program. This achievement is a testament to our commitment to hands-on, practical education.
At VSD, our role extends beyond traditional education. While we didn’t invent EDA tools or design flows, we’ve made them accessible to a wider community. Our mentorship has been instrumental in the development of over 50+ Analog/Digital IPs and solutions. Impressively, 20+ of these have successfully transitioned from concept to Silicon – a clear indicator of our effective approach and the high quality of work produced under our guidance.
We pride ourselves on fostering a community-based revolution in the Semiconductor Industry. By democratizing access to advanced tools and knowledge, VSD is not just educating individuals; we are building a community of innovators poised to lead the next wave of advancements in the semiconductor sector. With VSD, the future of VLSI Design is not just being written; it’s being rewritten by a passionate and empowered community.
Media Coverage
RISC-V Roadshow on SHAKTI Ideology
Prof. V. Kamakoti,
Director of IIT Madras
Boards
VSDSquadron RISC-V and VLSI Chip Design Educational Board
Buy Now
Last Date : 30 April 2024
Exclusive lifetime Access to a comprehensive 40-hour lab intensive module covering RISC-V, VLSI Physical Design, Static Timing Analysis and CMOS Circuit Design
Also available on
