Why VSD-IAT Workshop ?

VSD is proud to announce a series of high-intensity lab-based RTL2GDS VLSI tapeout based workshops – specially hand-crafted for freshers and mid-level experienced people. The way it has been successfully working over the last few years was because all workshops start at a very basic level on Day-1 (like from mux, gates) and gradually the complexity increases as you proceed along Day 2,3,4,5.

Why VSD tapeout workshops are so popular is because they are easily scalable for 200+ users per cohort and close to 2000+ users per month, while giving personal attention to every participant through LIVE 24/7 QnA over slack channel.

This has actually removed one layer of confusion which is pretty common around all VLSI freshers using multiple technology nodes for multiple topics of RTL2GDS. In reality, while doing chip design and tapeout, we cannot and should not be changing technology nodes. This is something which is made pretty clear in first day of the workshop and through the entire duration of the workshop, through labs.

All workshops automatically enable every participant to create a personalized report (and hence a resume) which can be taken directly to the technical manager for recruitment.

VSD workshop participants have gained a lot from this process, so you never know – after the above 7-weeks of workshop, you might be the next person which industry is looking for

Finally, VSD instructors and teaching assistants are so much well versed and experienced with Skywater 130nm tapeout process, that your design might be just the next one which can be converted to a real chip !!

VSD-Intelligent Assessment TechnologySpecsPDSTAPVCircuit DesignIP DesignFPGA GDSII TapeoutFPGA FlowASIC FlowPLL IPBandgapIPSynth

VSD-IAT Workshop using Synopsys tools

VSD-IAT and VSD-HPD Mentors

VSD Teaching Assistant


  1. Sir I am BTech (ECE) final year student. I want to design SRAM memory from rtl to layout…on the basis of my theoretical knowledge and I have completed many physical design courses (by you) on udemy and full course in physical design from NPTEL . Sir please guide me …after making netlist by using verilog..what should I do for physical design.

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