Mission : Design a Chip at $0

We’re supporting a community where more than millions of people learn, share, and work together to build a chip. At VSD, where we always promote “open source,” we’re promoting about a proven method of collaborating to create technology. The freedom to see the design, to learn from it, to ask questions and offer improvements: This is the open source way.

VSD partners with open source developers in hardware domain to build the vsdflow that will provide platform to community for designing a chip at $0.Open source developers partner with VSD for our approach to build content centric, research oriented flow to build a design and community.

VSD has partnered with EICT Academy IIT Guwahati to conduct online workshops and training program to develop the skilled open source community !!

Practice Areas:

  • RTL design, Synthesis and Verification
  • SoC planning and Design
  • Sign-off analysis
  • IP Design
  • CAD/EDA automation and basic UNIX/IT
  • RISC-V, Machine intelligence in EDA/CA

VSD expertise

VSD team had held several technical leadership positions at Qualcomm's Test-chip business unit. VSD founder, Kunal Ghosh, joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips. In 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. He holds a master’s degree in electrical engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.

VSD team is an open-source EDA evangelist and has IEEE paper on “Technology mediated tutorial on RISC-V CPU core implementation and sign-off using revolutionary EDA management system (EMS) — VSDFLOW”

VSDFLOW  is  an  automated  solution  to  programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW  is  completely build  using open-source EDA tools and open-source IP’s, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

To propagate vsdflow among students community and increase its usage, VSD has developed 30 online course including labs which will an hands on experience to anyone interested to learn opens source concepts and design a chip.

Current Reach of VSD online Courses:

 As of 2019, VSD and its partners have released 30 online VLSI training courses, all using open-source EDA tools/IP’s and was successfully able to teach ~22K students around 135 countries in 42 different languages, through its unique info-graphical and technology mediated learning techniques.

"When the best design works, great idea is born"

 

 

 

 

 

Kunal Ghosh

Digital and Sign-off expert & Co-founder

Qualcomm's Test-chip business unit

Cadence as Lead Sales Application engineer

 

 

 

 

 

Anagha Ghosh

Founder & Business Head

Project Manger TATA Power Company

University Training Partner :-EICT Academy, IIT Guwahati

About E&ICT Academy : MeitY has sponsored a scheme entitled "Scheme of Financial Assistance for setting up of Electronics and ICT Academies". Electronics and ICT Academy would aim to provide specialized training to the faculties of Engineering, Arts, Commerce & Science colleges, Polytechnics etc, by developing state-of-the-art facilities.

Academy has planned short term training programmes on fundamental and advanced topics in IT, Electronics & Communication, Product Design, Manufacturing with hands on training and project work using latest software tools and systems.

In addition, the Academy will conduct specialized/customized training programmes and research promotion workshops for corporate sector & educational institutions. It is envisaged that the Electronics and ICT Academy will become a central hub of activities on training, consultancy work and entrepreneurship programmes.

Webinar Partner

Rajeev has developed an open source EDA tool "Proton" while at Silverline Inc.

 

 

 

Steve Hoover is the founder of Redwood EDA.

 

 

 

Tim Edwards runs the website opencircuitdesign.com, dedicated to open-source EDA software and hosting such tools as magic, qflow, netgen, and xcircuit.

 

 

Rohit Sharma is Founder and CEO of Paripath Inc  He is passionate about many technical topics including Machine Learning, Analysis, Characterization and Modeling, which led him to architect guna - an advanced characterization software for modern nodes.

 

 

Tsung-Wei Huang,Research Assistant Professor, CSL & ECE,University of Illinois at Urbana-Champaign, IL, USA

 

 

 

Clifford Wolf, Architect of Yosys synthesis

 

 

 

Puneet Goel, Developer of Embedded UVM, Coverify Systems Technology

 

 

Recognition by University of Illinois

VSD Mentor's

Promode Kumar Ghosh, Director VLSI System Design Corp.Pvt.Ltd

 

 

 

Srikanth Jadcherla, Chairman and CEO of iMedrix, Mobile systems Guru, Technologist, Educator & Entrepeneur.

 

 

 

Ashok Kalbag,  Secretary at IUCEE , Secretary General at PanIIT India, Member at Vigyan Ashram.

 

 

 

Mohamed Kassem, Cofounder and CTO of efabless corporation.

Technology Partner

Paripath Technology (Guna EDA tool)

 

 

 

eFabless (design, verify and prototype IC design)

 

 

 

Makerchip ( Verilog design environment)

 

 

Coverify (Verify complex SoC designs)

 

 

We will be happy to hear from you.
Get in touch with us today and the Join the Community!!
Email id : contactvsd@vlsisystemdesign.com