VSD Community Silicon Tapeout

Open Source Hardware Journey Begins !!

A dream and a mission statement that was framed 10 years back by VSD and Efabless (or let us say, e-fabulous) has now taken a surprisingly good shape and IS FINALLY SILICON PROVEN. Release of Google/Skywater-130nm open PDK’s was really the final piece of entire VLSI training model puzzle.

Project Name

Student name and Github repo

Institute Name : IIIT Bangalore

Sequence detector_moore_machine(1011)

Pulse Width Modulated Wave Generator with Variable Duty Cycle

Sanampudi Gopala Krishna Reddy

https://github.com/sanampudig/iiitb_pwm_gen

RISC-V

Ring Counter

Clock Gating

Frequency Divider

Real-time clock

Universal shift register

101011 Sequence detector _Mealy_Machine

PISO shift register

Ring counter

Radix-2 4-Bit Booth's Multiplier

First Silicon proven Tapeout

Please join me to Congratulate Lakshmi S – MS ECE

Lakshmi had joined 5-day Workshop on VSD-IAT Physical Design and SoC design using open-source EDA tools which happened on 27th May’ 2020 and then RISC-V based MYTH workshop on 29th July’ 2020. Very soon, VSD noticed something incredibly unique within her when she submitted her pre-layout Git repo for avsdpll_1v8. It was quite evident, Lakshmi is here for the long run, and when internship finished, she was the first one with a fully completed post-layout Git repo using Skywater 130 PDK’s. Here is detailed Git repo: (GitHub is indeed the new resume)

https://github.com/lakshmi-sathi/avsdpll_1v8

VSD-IATTapeout Program Workshop SeriesSpecsSynthPDSTAPVStandard CellAnalog/DigitalIPFPGASept 2022Nov 2022PLL IPOct 2022Bandgap IPOct 2022Sept 2022Sept 2022SKY130 GDSII TapeoutFPGA FlowASIC FlowSept 2022

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