Tool related – VLSI System Design

VSDOpen announces new technologies for effective VLSI skill development-2

If you have been following VSDOpen for the last 5-years, the theme has been maintained – What VSD did last year and what VSD will do next year

VSDOpen2022 – Ground-level efforts to boost Semiconductor tapeouts and Skill Development

VSDOpen conference is an attempt to bring out some cutting-edge activities especially around open-source EDA with a special focus on skill development using open and proprietary tools. VSDOpen also focuses on milestones achieved by VSD in the past year, and some interesting projects which VSD will be working on in the next year. It’s like the VSD Annual Hands-on meeting where everyone is invited for free and allowed to rate us for our work 🙂

Why is a Physical Design workshop important for education?

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Hi Kunal

Traditional pieces of training have taken an orthogonal shift, post-release of open-source EDA tools and SKY130 foundry. This has brought a huge opportunity for semiconductor ed-tech companies like VSD to close a wide gap within many training companies that have shifted their curriculum from theoretical PDK to real PDK. If you are a student, who is reading this email, do not panic if you are not aware of PDK. This is something which we are covering in the workshop.

Random Verification in Hardware – A Primer

Join us to explore such concepts and more, where we use Python to leverage its library-rich environment feasible for verification using Vyoma’s UpTickPro platform, in this edition of Capture the Bug hackathon, organized by NIELIT, Calicut, mentored by IIT Madras, in association with VLSI System Design and Vyoma Systems.
Hackathon details – https://nielithackathon.in/

Opencores.org – Encyclopedia to begin the Hackathon

For the upcoming Capture The Bug Hackathon, participant is free to choose any Verilog Open Source design from any website/reference similar to that of OpenCores with appropriate licensing which is compatible with Icarus Verilog and also the Verilog code needs to be synthesizable.

Happy Verification!!!

Design Verification hackathon means what?

The working of digital computers, smartphones, etc all have some underlying basic logic manipulating just 0s and 1s to come up with interesting outcomes. With […]

Chip Tape-out – Not a dream anymore – VSD students prove it again

From nothing to Tapeout Ready basic designs – These 7 students have seen it all. Congratulations to all of them. Great start to their semiconductor career.
Here’s the link with their design details-

“What I did in the 5-day Advanced Physical Design workshop?” – Experiencing the “freedom within expanding boundaries”

I have been tracking opensource tools in backend flow and also VSD’s online programs like MYTH, Digital System Design, Modelling using Verilog etc. In the […]

What I did in 8-weeks-VSD Internship? – Open Source Power Analysis Tool Using Python

Power analysis has materialized as a principal theme in today’s world in semiconductor industries. As very large scale integrated circuit (VLSI) are far beyond from human ability because of complexity in nature. So to analyse power in these circuits we use open source computer aided tools, plenty of tools are available but most of them are costly. I designed an open source power analysis tool for the academic use. This tool gives out values of average and leakage power of any circuit by just giving the netlist of circuit file along with name of supply voltage as input. This tool is designed in python language.

VSD aims to tackle global chip designer shortage

Above article does talk about chip shortage, which is due to increased demand of consumer electronics like laptops, tablets, mobiles, which was never the case […]