Advanced Physical Design using OpenLANE/Sky130
Physical Design or PnR (Place and Route) is the core of any IC design cycle. From a RTL netlist to final tape-out, each phase of PnR brings it’s own challenges and surprises. “What are these challenges?” “What is the process?” “Can I build a chip of my own?”- If you have these questions and if you are eager to delve into the world of ASIC design flow..Wait no more!
With the announcement of Google-SkyWater’s first manufacturable open source 130nm process design kit (pdk), open source EDA world is no longer limited in scope to academic research and small scale projects only. This along with the conception of Openlane flow, a fully-automated RTL2GDSII flow, has made the dream of “an IC for all” a near reality.
So here’s announcing the ultimate workshop on SoC design planning in Openlane flow using the latest Google-SkyWater 130nm process node.
So if you want to –
- Design and characterize your own standard cell.
- Have a hands-on in the Physical Design domain.
- Generate a full GDSII from a RTL netlist.
-
Explore and contribute to open source EDA world.
This is the opportunity for you!!
Workshop Day wise Content :
Day1 – Inception of open-source EDA, OpenLANE and Sky130 PDK
- How to talk to computers
- SoC design and OpenLANE
- Starting RISC-V SoC Reference design
- Get familiar to open-source EDA tools
Day 2 - Understand importance of good floorplan vs bad floorplan and introduction to library cells
- Chip Floor planning considerations
- Library Binding and Placement
- Cell design and characterization flows
- General timing characterization parameters
Day 3 - Design and characterize one library cell using Magic Layout tool and ngspice
- Labs for CMOS inverter ngspice simulations
- Inception of Layout – CMOS fabrication process
- Sky130 Tech File Labs
Day 4 - Pre-layout timing analysis and importance of good clock tree
- Timing modelling using delay tables
- Timing analysis with ideal clocks using openSTA
- Clock tree synthesis TritonCTS and signal integrity
- Timing analysis with real clocks using openSTA
Day 5 - Final steps for RTL2GDS
- Routing and design rule check (DRC)
- PNR interactive flow tutorial
Refund Policy:
- Last date to apply for refund is 20 January 2021.
- Students absent during Workshop NOT eligible for Refund.
- Yosys – for Synthesis
- OpenLane - for RTL2GDS
- NgSpice - for Characterisation
- Magic – for Layout and Floorplanning
- OpenSTA – Pre-layout and Post-layout Static timing analysis
Reference Design Base:
- RISC-V based PicoRV32 SoC
Refund Policy:
- Last date to apply for refund is 20 January 2021.
- Students absent during Workshop NOT eligible for Refund.
- Virtual Coach platform with expert instructor guidance
- Cloud-based dedicated Virtual Machine to perform Design labs
- Intelligent Assessment Technology (IAT) and Project allocation
- 24 hours Lab access for 5 days and Instructor assistance on demand
- Run EDA scripts, evaluate VLSI layout and Timing analysis reports on platform.
Refund Policy:
- Last date to apply for refund is 20 January 2021.
- Students absent during Workshop NOT eligible for Refund.
Instructor Profile:
Kunal Ghosh, co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd., Kunal pioneers in the field of online open-source EDA (qflow & openroad)/open-source hardware (specially RISC-V) design and learning. Currently, Kunal owns around 32 high-quality VLSI online courses in and around open-source EDA/hardware, which is being consumed by around 28700+ students around 141 countries. Apart from trainings, Kunal has also worked with IIT Madras and IIT Guwahati on open-source activities and design projects. Currently, Kunal and his team are working on developing high quality open-source Analog/Digital IP’s which would be first one’s in the field of open-source hardware design. Prior to VSD, Kunal has worked with Qualcomm and Cadence, in field of SoC design. Kunal has done his Masters at IIT Bombay in field of VLSI & Nano-electronics, with specialisation in Sub-100nm Electron Beam LithographyOptimisation techniques
Guest Instructor Profile:
Timothy Edwards, Founder Opencircuitdesign.com and SVP at Efabless.He is Analog VLSI designer and collecting and developing open-source EDA tools for over 27 years, He worked for the Johns Hopkins Applied Physics Lab, startups MultiGiG and Analog Devices. He has developed open-source EDA software tools such as Magic, Qflow, Netgen, and Xcircuit.
Mohammed Shalan, Associate Professor, American University in Cairo.He is Founder of CloudV.io, The Open Cloud-based Digital ASIC/FPGA Design Environment, Fault, the only open-source DFT solution. He worked as Embedded Systems Architect for Automotive and Mobile (Mentor Graphics), Embedded Software Manager (MindSpeed and Mentor Graphics), Digital ASIC Designer (Freescale), SoC Consultant, Digital ASIC PnR Consultant.He holds Patents- Power Profiling for Embedded System Design, Power System Optimization and Verification for Embedded System Design.
Teaching Assistant Profile:
Ahmed Ghazy, fresh Computer Engineering graduate from the American University in Cairo with a minor in Mathematics. Currently working at eFabless where he worked on the OpenLANE flow 1 for over a year now and made many contributions to open-source EDA tools including the OpenROAD tools, magic, and netgen.Other research interests include computer security and cryptography, data structures and algorithms, and combinatorics.
GitHub is the new Resume for VLSI industry
GitHub is indeed the new RESUME for VLSI industry. Really, if you are recruiting person and looking forward to judge a new candidate for a role in company, ask for GitHub project link. Projects written on resume and projects available on GitHub by a candidate will immediately give you an idea about his/her perseverance, dedication, sincerity, productivity and amount of hard-work he/she can put inside a project.
Please have look at few of our Previous Workshop Github Repos
SoC Design Workshop Repos | |
Name | Github Link |
Akil M | |
Renuka Sunder | |
NAMRATA P. SINGHA | |
Chaitanya Somanchi | |
Francisco de Assis Brito Filho | |
Dipta Chaudhuri | |
Ruthvik Kuram | |
Sai Swaroop Mishra | |
Pavankalyan Motamarri | |
S Skandha Deepsita | |
Sai Bruhath Kotamraju | |
Ramanpreet Kaur | |
Kanishk Barhanpurkar | |
Ashish Patil | |
Refund Policy:
- Last date to apply for refund is 2oth January 2021.
- Students absent during Workshop NOT eligible for Refund.
IP Name - 130nm PLL Clock Multiplier IP
8x PLL Clock Multiplier IP on the Google-Skywater 130nm node.
Tested through spice simulations on skywater 130nm tt corner at room termperature
Generates 8x Multiplied Clock.
Please read more about Tapeout : https://www.vlsisystemdesign.com/tapeout/
Ready for 5-day VLSI workshop + 8-week internship?
- Workshop + internship important dates:
1week workshop using OpenLANE/Skywater 130nm PDK’s (22nd – 26th January 2021) - 1 week for Git resume (27th – 31st January 2021)
- 8-weeks Research IP design internship using Sky130nm PDK’s (Starting 1st Feb 2021, only for participants who successfully complete above workshop, with a valid Git Repository)
Format: Cloud based Virtual Training Workshop
Duration - 5 Day
Cost : $59 + 18% GST
Date : 22-26 January 2021
Last date for Registration: 20 January 2021
Refund Policy:
Last date to apply for refund is 20 January 2021.
Students absent during Workshop NOT eligible for Refund.
Registration :
Indian Participant
International Participant