Sfal – VLSI System Design

Advanced Certification Program

SoC Design and Implementation

Joint program by SFAL and VSD

Overview

The 12-week SoC Design and Implementation course starts with 6 weeks covering semiconductor design basics like floorplanning, placement, CTS, routing, optimization, and verification. Students learn everything from chip size estimation to signal integrity fixes. Following this, they choose a specialization topic, allowing for targeted learning in a specific area of interest under expert guidance.

The course then shifts to a 4-week, in-depth exploration of industry-grade concepts, led by professionals and culminating in a design project that mirrors real-world challenges. The final 2 weeks focus on professional skills, including Github documentation and internship selection, equipping students for the semiconductor industry.

This blend of foundational learning, specialization, and practical application, guided by industry experts, prepares participants for successful careers in SoC design and implementation, balancing theoretical knowledge with hands-on experience.

This program is your gateway to:

Mastering the complete SoC design process, from floorplanning to physical verification.
Personalizing your learning journey by selecting a topic for specialization.
Gaining insights from industry experts through an in-depth, real-world design project.
Enhancing your professional portfolio with Github documentation skills.
Securing potential internship opportunities in the semiconductor industry.

Seize this unparalleled opportunity to transform your passion into expertise!

8 compelling reasons to join this workshop

Curriculum

Floorplanning : Core and die size, I/O placement, power planning, block placement
Placement : Initial techniques, optimization cycles, timing-driven adjustments
Clock Tree Synthesis (CTS) : Clock regions, skew minimization, implementation
Routing : Global and detail strategies, via insertion
Post-Placement Optimization : Buffer insertion, gate sizing, logic repositioning
Post-Route Optimization & Physical Verification : Timing closure, power optimization, signal integrity, DRC, LVS checks
Specialization Topic Selection
In-depth Project by Industry Experts

Join us for this transformative journey and turn your fascinationinto tangible skills in the ever-evolving world of IC design!

Tools - Synopsys

Design Compiler : For high-quality synthesis of HDLs into gate-level representations.
IC Compiler : A comprehensive place and route solution ensuring optimal chip layout.
PrimeTime : For sign-off quality timing analysis, ensuring your design meets its timing requirements.
StarRC : The industry standard for parasitic extraction, vital for accurate post-layout simulation and analysis.
HSPICE : The gold standard for accurate circuit simulation, crucial for design verification.
Custom Compiler : Tailored for designing custom integrated circuits with precision and efficiency.
IC Validator : An essential tool for physical verification, performing DRC (Design Rule Checking) and LVS (Layout vs. Schematic) checks to ensure the design meets all manufacturing specifications.

Projects

VSD Participants profile

Delivery Mode

We’ve tailored every aspect of the program to ensure an effective and enjoyable learning journey:

Eligibility

Fresher or recently graduated or experienced professionals looking to brush fundamentals.

Atleast BE/BTech/ME/MTech or equivalent.

About VSD

Online Beginner Course

RTL GDSII VSD-IAT Workshop

VSD Community Based Silicon Tape Out

Analog & Mixed Signal IPs

VSDOpen Online Conference

Unique Global students

VSD Hackathon Participants

VSDSquadron Educational and Dev Kit

VSD, standing as a trailblazing Semiconductor EdTech company and a community-based Technology Aggregator, is revolutionizing the landscape of VLSI Design. With the belief that “Creativity is just connecting things”, VSD has mastered the art of linking the right resources with the community. This unique approach has sparked a significant transformation in the VLSI Design process.

Over the past decade, VSD has made remarkable strides in the open-source semiconductor domain. Our journey includes the development of comprehensive training content, empowering students to design silicon-grade IP/SoC. Notably, we’ve successfully guided these projects through the tapeout cycle via the Google open shuttle program. This achievement is a testament to our commitment to hands-on, practical education.

At VSD, our role extends beyond traditional education. While we didn’t invent EDA tools or design flows, we’ve made them accessible to a wider community. Our mentorship has been instrumental in the development of over 50+ Analog/Digital IPs and solutions. Impressively, 20+ of these have successfully transitioned from concept to Silicon – a clear indicator of our effective approach and the high quality of work produced under our guidance.

We pride ourselves on fostering a community-based revolution in the Semiconductor Industry. By democratizing access to advanced tools and knowledge, VSD is not just educating individuals; we are building a community of innovators poised to lead the next wave of advancements in the semiconductor sector. With VSD, the future of VLSI Design is not just being written; it’s being rewritten by a passionate and empowered community.

Instructor Profile

Meet Your Guides to the World of VLSI Design

Kunal Ghosh

FAQ

What's the cost to register?

We've set a special discounted fee of INR 75000 + 18% GST ~~(INR 1,80,000)~~. Our aim is to make Synopsys EDA tools and PDKs accessible for various purposes such as college projects, PhD research, semester lectures, and keeping up with industry trends.

Can I participate according to my schedule?

Absolutely! The program is hosted on the cloud platform, offering flexibility to log in at your convenience. The platform is accessible 24 hours a day during the two weeks duration of the program.

Can experienced system designers join to refresh their knowledge?

This program is primarily designed for newcomers to the field of VLSI. However, experienced professionals interested in sharing their expertise with students are more than welcome to join.

Will I have access to the program content after it ends?

Yes, you will receive lifetime access to all lab files. However, access to the videos and the platform will end with the program.

Do I need to install any software for the labs?

No, all labs will be conducted on the cloud platform using a Linux Terminal with all necessary tools pre-installed. Post-program, we will provide scripts for you to install these tools on your own computer for further practice and revision.

How are the labs distributed for this program?

Labs will be shared via a virtual box image. You'll receive detailed instructions on accessing and using this image a day before the program starts.

What platform is used for the lectures?

Lectures will be delivered through the LMS platform. This platform allows you to access course materials and interact with the content at your own pace.

Is there support available during the program?

Yes, our instructors and Teaching Assistants are available 24/7 on Slack throughout the 12 Weeksprogram to answer questions, provide clarifications, and help.

Is there a specific time for addressing urgent issues?

Indeed, there's a daily one-hour sync-up call during the program. This is a valuable time for discussing any immediate issues, challenges, and for receiving direct guidance from instructors and TAs.

Is the program flexible for asynchronous participation?

Yes, the program is hosted on a cloud-based platform, allowing you to access materials and complete tasks at your convenience, ensuring flexibility in your learning schedule.