Events


Recent Events : –

Webinar on “SoC Reference Design of the PicoRV32 RISC-V Microprocessor” – With Kunal Ghosh, Tim Edwards & Mohamed Kassem

After successful webinar on Making of Raven Chip, this time we take the chip forward and implement using end-to-end opensource EDA tools, and all on efabless cloud. What does this mean to us? It means, you can start innovating on a design, build RTL and do synth/PD/LVS/DRC all using opensource EDA framework and not pay a single penny for license.

The big question How is this possible?

Thereby, I welcome you all to my next (follow-up) webinar with Tim Edwards and Mohamed Kassem on 2nd June and below is the

Webinar Agenda:

Part 1: IP digital flow and chip integration on efabless.com

  1. The efabless model (recap from Part 1)
  2. The efabless platform:
  3. The (updated) Marketplace
  4. CloudV (continued work in progress)
  5. Open Galaxy (updated apps)
  6. The Raven chip project (update)

Part 2: Digital synthesis with CloudV

  1. The CloudV platform
  2. CloudV ongoing development
  3. Interactive CloudV tutorial:
  4. Clone an open-source “soft” IP
  5. Synthesis using CloudV
  6. Export to Open Galaxy

Part 3: Synthesis flow on Open Galaxy

  1. Synthesis
  2. Placement
  3. Routing
  4. DRC
  5. LVS
  6. Interactive tutorial:
  7. Clone the raven_spi IP block
  8. Run through “qflow” synthesis steps to layout

Part 4: Full chip integration on Open Galaxy

  1. Floorplanning the core
  2. Generating and connecting the padframe
  3. Placing components
  4. Top-level signal routing
  5. Top-level power routing
  6. Interactive tutorial: Using the layout tool for top-level integration

Tips and tricks for using the Magic VLSI layout tool efficiently

Part 5: Full-chip verification on Open Galaxy

  1. Additional requirements: Substrate contacts, antenna tie-downs, etc.
  2. Final DRC
  3. Final LVS
  4. Interactive tutorial: Using the LVS tool for top-level verification

Tips for understanding LVS errors and how to fix them

Part 6: Challenge

Design and verify a small chip in 0.18 m technology

Padframe provided

1.8V only (no voltage regulator), applied CMOS clock (no oscillator)

  1. Create a simple verilog function (details TBD)
  2. Synthesize, place, and route the digital block
  3. Compose top level from padframe and digital block
  4. Route core to pads
  5. Verify DRC and LVS

Instructor Details:

Tim Edwards

Tim Edwards has been doing analog VLSI design and collecting and developing open-source EDA tools for over 25 years.  He has worked for the Johns Hopkins Applied Physics Lab, startups MultiGiG (bought by Analog Devices) and most recently, eFabless.  He runs the website opencircuitdesign.com, dedicated to open-source EDA software and hosting such tools as magic, qflow, netgen, and xcircuit.

Mohamed Kassem

Mohamed Kassem is the cofounder and CTO of eFabless corporation. Prior to launching eFabless in 2014, Mohamed held several technical and global leadership positions within TI’s Wireless Business Unit. He joined TI in 2000 at the beginning of the digital telephony revolution fueled by the unprecedented integration of major phone functions on a single SoC. He led the first development of 45nm, 28nm analog & mixed-signal IP functions for wireless applications processors. Mohamed holds a masters degree in electrical engineering from the University of Waterloo, Ontario, Canada.

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Webinar “Distributed timing analysis in 100 lines code” on 26th May 2018 by Tsung-Wei Huang

We all know timing analysis is a really important task in overall chip design flow and its so complex and difficult task. The chip that we incorporate today has billions of transistors, resulting timing analysis runtime is tool large. Also, we need to analyze timing under different conditions, so its not just a single run that you get a final result. While there are several solutions to mitigate this computation issue, the problem is most of the work is architecturally constrained by single machine. And as design complexity continue to grow larger and larger, we have to add more and more CPU and memories to the machine, but not very cost-efficient
There are multiple places, we can introduce distributed computing to timing and major motivation is to speed up the timing closure. We have to analyze timing under different range of conditions, typically quantified as modes (test mode, functional mode) and corner (PVT). The number of combinations (timing views) you have to run is typically increasing exponentially with lower nodes. That’s where you need to need to distribute timing analyses across different machines.
So let’s distribute it and do it within 100lines of code using DTCraft – A High-performance cluster computing engine. Welcome to the webinar on “Distributed timing analysis within 100 lines of code” on 26th May, 9am IST (Limited Tickets). In my last webinar, all tickets sold out in 2 days, so you might want to reserve your seat TODAY
Speaker: Tsung-Wei Huang
Tsung-Wei Huang is Research Assistant Professor, in Department of Electrical and Computer Engineering at University of Illinois at Urbana-Champaign, IL, USA. He has done his PhD in Electrical and Computer Engineering at UIUC. He holds 2 patents and more than 30 Conference and Journal Paper publications.

Recorded Version for people who missed it !!

VSD – SoC Design of the PicoRV32 RISCV micro-processor

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Webinar “RTL Synthesis QnA webinar” by Clifford Wolf and Kunal Ghosh on 19th May 2018

Hey There,

Our next webinar is slightly different one. It’s a Q&A webinar on RTL Synthesis, by Clifford Wolf. Clifford is architect of ‘Yosys’ which is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Clifford will be answering below 23 queries on RTL synthesis. Entry to this 2-hour webinar is FREE, recording is paid. So, buy it, if you like it.

This webinar opens 2 new opportunities, one – a chance to interact with architect of Synthesis, two – a chance to get your question in TOP25 list. Since we have already started receiving queries, make sure you draft challenging queries.

Below TOP23 query submissions are directly eligible for certificates from our company “VSD Corp. Pvt. Ltd.” All the best and happy learning.

Note of Appreciation – I have worked with Clifford in my course on TCL programming Part 1 & 2, and really Thank him for all his guidance for making of TCL programming course.

Recorded Version for people who missed it !!

VSD – RTL Synthesis Q&A Webinar

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Webinar  on “Library Characterization and modelling Part 2” 28th April – 9am to 1pm IST with Kunal Ghosh & Rohit Sharma

Webinar overview:

We are going to present “Characterization with GUNA : A characterization tool by Paripath”. We will go through the characterization flows – flows which are popular for standard cells, memories, IP’s.
Within that, we will cover timing, noise, power and variation as 4 main topics of the characterization. Each one of those is expected to have a lab, where instructor will run GUNA as a standalone software and generate the models.
We will also clarify some concepts on chip variation, like what kind of variation exists (AOCV, POCV, SBOCV, LVF, etc), how do we tackle/model that, shortcoming of each on of this models and how do we move down the node, changing our model to account for some of the facts that show up in every transition to a new advanced node

So lot of exciting thing to be presented, and, the biggest thing about this webinar is the Instructor himself – Rohit Sharma.

 

About Instructor:

Rohit Sharma is Founder and CEO of Paripath Inc based in Milpitas, CA. He graduated from IIT Delhi. He has authored 2 books and published several papers in international conferences and journals. He has contributed to electronic design automation domain for over 20 years learning, improvising and designing solutions. He is passionate about many technical topics including Machine Learning, Analysis (above image), Characterization and Modeling, which led him to architect Guna – an advanced characterization software for modern nodes. He currently works for Paripath Inc.

Date & Time : –  28th April – 9am to 1pm IST

Recorded Version for people who missed it !!

VSD – Library characterization and modelling – Part 2

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Webinar on “Machine Intelligence in EDA/CAD” on 31st March, 9 AM IST with Kunal Ghosh and Rohit Sharma

We start with Electronic design automation and what is machine learning. Then we will give overall introduction to categories of machine learning (supervised and unsupervised learning) and go about discussing that a little bit. Then we talk about the frameworks which are available today, like general purpose, big data processing and deep-learning, and which one is suitable for design automation. This is Machine Learning in general with a focus on CAD, EDA and VLSI flows.

Then we talk about Applied Theory (data sets, data analysis like data augmentation, exploratory data analysis, normalization, randomization), as to what are the terms and terminologies and what do we do with that, accuracy, how do we develop the algorithm, essentially the things that are required to develop the solution flow, let’s say, you as the company wants to add a feature in your product using machine learning, what you would be doing, and what your flow will look like and this is what is shown as pre-cursor of flight theory as what you should be looking out.

And then we start with regression, which is first in supervised learning. In the regression, we will give couple of example, like first is resistance estimation, second is polynomial regression which is capacitance estimation. For resistance estimation, we have the dataset from 20nm technology. And finally, we go on to create a linear classifier using logistic regression.

Next will be conditionality reduction, meaning, you have a large dataset and how to you reduce the size of that so that you can run on a laptop or even on your cell phone. Then there is a big example of that. Everything has mathematics behind that, this won’t be a part of the webinar.

[Follow-up webinar] Then we will move on to Deep Learning and finally we plan to have feed forward neural network, where we create couple of applications using neural networks. The first one is binary classification of cells, like you have library and we will design a neural network which can figure out a cell that’s give to it is combinational or sequential. And then, we make it broader and bring about 10 classes. So, there are 10 different type of cells (we can label them) and without giving any other information, can the neural network be designed to handle those 10 classes and can figure out which cell it is out of those 10 classes

Webinar presents a hands-on approach with session on GPUs, solving design automation problems with modern machine intelligence techniques by including step-by-step development of commercial grade applications including resistance estimation, capacitance estimation, cell classification and others using dataset extracted from designs at 20nm.

It walks the reader step by step in building solution flow for EDA problems with Python and Tensorflow.

It is organized to serve as a compendium to a beginner, a ready reference to intermediate and source for an expert.
 Intended audience
  1. Design automation engineers
  2. Managers
  3. Executives
  4. Research professionals
  5. Graduate students
  6. Machine learning enthusiasts
  7. CAD developers, mentors

Webinar Agenda

  1. Intro to Machine Learning in EDA/CAD – 10 Min
  2. Categories of Machin Learning – 10 Min
  3. Machine Learning Framework – 40 Min
    1. Python Primer
    2. Introduction to Tensorflow
  4. Applied Theory – 30 Min
  5. Regression – 90 Min
  6. Classification – 60 Min

Speaker details : Rohit Sharma

Rohit Sharma is Founder and CEO of Paripath Inc based in Milpitas, CA. He graduated from IIT Delhi. He has authored 2 books and published several papers in international conferences and journals. He has contributed to electronic design automation domain for over 20 years learning, improvising and designing solutions.

He is passionate about many technical topics including Machine Learning, Analysis, Characterization and Modeling, which led him to architect guna – an advanced characterization software for modern nodes.He currently works for Paripath Inc.(www.paripath.com)

Recorded Version for people who missed it !!

VSD – Machine Intelligence in EDA/CAD

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Webinar on “Making the Raven chip: How to design a RISC-V SoC”? – With Kunal Ghosh

Building a chip is like building a city…
This was the mantra with which we started our company in 2011. Now that we have covered major components of chip designing through our online courses, I think this is the right time to move from “chip designing” to “chip planning”

Chip Planning involves lot of decision making like, analog peripheral (ADC, DAC, POR, etc.), digital peripheral (UART, flash controller), memory mapping, top level connections like pad-frame, level-shifters, GPIO and many more.

Do you want to know what it is like to build a city? Enroll in webinar on 3rd March from 9am to 1pm IST with myself, Tim Edwards and Mohamed Kassem. Details of registration link will be published soon.

This is the perfect webinar for to grow and stay ahead of curve in Semiconductor and Chip design.

Webinar Description :

  1. .Raven SoC overview
  2. Run-through of Raven files:
    (A) picorv32
    (B) raven_spi
    (C) raven_soc
    (D) digital peripheral (UART, flash controller)
    (E) memory (SRAM)
    (F) analog peripheral (ADC, DAC, POR, etc.)
    (G) padframe
  3. Further description of SoC and choice of connections between blocks
  4. Memory map description
  5. Top-level connections: padframe, level shifters, multiplexers
  6. Testbench C code
  7. Testbench verilog code
  8. Make file run-through
  9. Running test bench series (GPIO, ADC, DAC, UART)
  10. Example:  Create a new testbench to test bandgap voltage and use bandgap as reference to test the comparator.
  11. Example:  Run the new test bench and verify operation.
  12. Overview of synthesis process
  13. Challenge:  Add a general-purpose timer/counter module to raven_soc
    (A) driven from select able sources:
    (i)   master clock
    (ii)  crystal clock
    (iii) external clock
    (iv)  RC oscillator output
    (B) 32 bits
    (C) Timer output routed to GPIO or interrupt
    (D) Counter output memory mapped
    (E) Control values are the amount to add to the counter per clock cycle and the value at which to toggle the timer output.
    (F) One-shot or continuous
    (G) Continuous mode may restart at zero or wrap around.

Recorded Version for people who missed it !!

VSD – Making the Raven chip: How to design a RISC-V SoC

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Pipelining RISC-V with Transaction-Level Verilog Webinar on 10th Feb 2018

Pipeline implementation – Which one is better? And Why?

Have you implemented a processor using Verilog? Which was the most important part of your implementation? What was your code size in Verilog? What if, we told you that you can reduce your verilog code size by about 3.5x by a new technology? What if, we told you that you can create any digital sequential logic you can dream up faster than you ever thought possible, all within your browser, probably Google Chrome?How about a ‘change’? Change the way you used to write your verilog code. Change the way you used to implement Pipelining for your processor. Change is the only “constant”Did this blog make you think? I encourage and welcome you to think in the right direction with experts from this field in my next webinar on “Pipelining RISC-V with Transaction-Level Verilog” on 10th Feb’ 2018. Just like my any previous webinars, even in this one, you will be able to interact with industry experts directlyAnd this time, we have instructors all the way from Greater Boston Area, US, with more than 18+ years of experience in the field of “Logic Design and Verification”All I can say is, me and participants who will be attending this webinar, will be “blessed”. I would re-iterate, just like my previous webinar emails, “recording is good, but LIVE is best”Stay tuned for tickets link and more about this webinar!!!Happy Learning…

Recorded version of Webinar who missed LIVE !!

VSD – Pipelining RISC-V with Transaction-Level Verilog

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Physical design webinar – 20th Jan – With Kunal Ghosh


What if I told you, you can design chip without installing any tools on your laptop?What if I told you, you can design chip on cloud, just like Amazon eFPGA?What if I told you, you can design chip for FREE?Don’t believe it…Well, attend my first physical design webinar on 20th Jan, and stay tuned to below link for more updates:This will be first ever webinar, where we will bring in industry EDA expert and EDA tool architect as support, while myself driving the webinarLearning something new is always good, as this might just what will happen in few years from now. (Amazon eFPGA – where you can setup FPGA environment on cloud and run your simulations – has proven that). Something similar will happen for back-end physical designThis year, we will begin with something new in the field of chip design, and let this webinar be the start…Like my all other webinars, expect a humongous discussion and interaction with experts.

Recorded version of Webinar who missed LIVE !!

VSD – Physical Design Webinar using EDA tool ‘Proton’

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Timing ECO webinar on 6th Jan…. Lets produce better chips

First, lets define better? Better in terms of Power. Performance and AreaEvery VLSI engineer, an RTL architect, or Lead Synthesis Engineer, or Senior Physical Designer, or Director of Signoff timing analysis practically everyone is doing timing ECO at every step of their flow. I, being a part of Signoff timing analysis and Physical Design world, am doing ECO almost every day, and so I understood that its more than adding buffer and upsizing/downsizing cells.All the factors or ways shown in above image impacts either dynamic power or short-circuit power or leakage power. The question is, do you know why do we still do it? Do you know how can we still do with minimally impact on other parameters? Yes, No, Dont Know.Its time to unveil more than 15 strategies to do timing ECO and below are few of them

  1. Routing congestion aware timing ECO
  2. Path based analysis ECO for selected endpoints
  3. Replicated modules based timing ECO
  4. Legalized timing ECO
  5. Margin based timing ECO

.and many moreSee, I told you, timing ECO is more than just adding buffers and sizing cells.Do you want to know all the strategies? Do you want to be a better timing engineer? Engineering includes tons of changes and modifications from inception to final product. Hence its called Engineering Change Order (ECO)Join the webinar on Jan 6th 9am to 12pm IST. Inviting students and professionals from India, US, Egypt, UK, and all over the world

Recorded version of Webinar for people who missed LIVE !!

VSD – Timing ECO (engineering change order) webinar

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How open source will begin innovation? STA Webinar :-Analyze your chip timing for FREE

Highlighting VSD’s technique to use open source tools for performing Static timing analysis leading to innovative design and cost effective solutions for Chip designers.VSD shows the technique to analyze a design using an Opentimer tool, which is used to do block-based analysis, path-based analysis, cppr, incremental timing, and multi-threading. Our methods are extremely fast and accurate to analyze large-scale designs.This webinar highlights the merits of Open source EDA tools to bring innovation in the Chip industry, and will also show our methods to learn & design on your PC and also enables higher performance at zero cost.
Recorded version of the Webinar for people who missed LIVE !!https://youtu.be/0dffOwNQdBg

VSD – Static Timing Analysis (STA) Webinar

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STATIC TIMING ANALYSIS (STA) WORKSHOP

Let’s begin with Second expert workshop in STA, after completing a full energy packed first workshop filled with freshers, professionals and also expertise in the field.VSD workshops are community events, where like-minded individuals get together, learn, practice and share ideas on what it take to build a design using open source EDA tools, also how to develop productive work culture with highly engaged designers.Following a knowledge ice-breaker and an innovative designing using open source tools, Lets have some more practice session to build a structure and to represent how an energetic community work towards developing a great CHIP DESIGN !!

First ever STA workshop using open-source tools in Bangalore!Static Timing Analysis (STA) is used at each stage of physical design. I have been very successful in physical design field at Qualcomm and Cadence, by doing STA first. STA is an art that can help you carefully craft the locations of your logic cells and route them. Do you want to know how it’s done? Welcome to my first ever workshop on STA and I can promise you I will change your perception towards STA and IC design for the good….

ORCONF 2017 – An Olympic Like Platform for Open-source

This time ORCONF is happening at Hebden Bridge, England, from 8th September to 10th September 2017.So, if you are a part of my community and if you stay somewhere in UK, we can catch-up at the conference at Hebden Bridge

Open-source EDA community building using technology-mediated learning

Kunal will talk about a novel technique of building open-source hardware community using adaptive and adaptable learning mode with open-source EDA tools. The gap confronted here is shortfall of guidelines and support systems to use these tools, and one architecture that connects complete design to all tools. VSD has been attempting to fill this gap by blending the learning and practicing methods through online video courses with the goal of building a large community across the globe who are designing and innovating using open-source tools.

Presenter: Kunal Promode Ghosh of VSD

An automated C-to-GDS flow using open-source EDA tools for medium-sized SOC design and implementation

A poster presentation on a complete C to GDS flow using open source tools demonstrated on a multi-million gate design.

Presenter: Kunal Promode Ghosh of VSD

Stay tuned for the upcoming Workshop & Webinar conducted by VSD

Register here and we will keep you posted with the dates of the Workshop & Webinar

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