Welcome to VSD community events !!
VSD-IAT cloud based 5 days workshop on “RISC-V based MYTH (MYTH – Microprocessor for You in Thirty Hours)” 29 July to 2 August 2020 for All Time Zone
VSD-IAT: RISC-V based SoC design using open-source EDA 27-31 May 2020 for All Time Zone
Let Knowledge Win !! webinar series by our “Knowledge Sharing Hero”
Recent Events : –
VSD-IAT: RISC-V based SoC design using open-source EDA 27-31 May 2020 !!
VSD comes to MUMBAI on 19th February 2020 !!
Online Workshop Physical Design using Synopsys ICC in association with EICT Academy IIT Guwahati on 20-24 January 2020 Only for Students currently studying in Indian Universities
“Transforming Silicon Industry Through Open-source” talk at Silicon Institute of Technology on 30th December 2019
Winter FDP on “VLSI SoC Design using Open Source EDA” on 16-20 December, 2019 at MNIT Jaipur
Second Online conference in VLSI Industry VSDOpen Conference 2019 on 19th October 2019
Keynote and Demo Slides : https://www.vlsisystemdesign.com/vsdopen-2019-keynote-virtual-demo/
Online Certificate Training Programme on “Hands-on Functional Verification using Embedded UVM” (14-18 October 2019 LIVE Streaming ONLINE) in association with EICT Academy IIT Guwahati and Coverify System Technology
RISC-V enters India and VSD personally invite you…
Another chance, another medium, another platform for us to catch-up personally…. (You might want to forward this email to your colleagues staying close-by any one of below cities, and encourage them to attend this free event to learn more about RISC-V ecosystem in India)
We would like to invite you to attend one of the SiFive & Open-Silicon Tech Symposiums taking place at six different locations throughout India in August. See map in below image for exact locations and date of events.
I would be presenting a very important tutorial, which closely connects open-source ISA implementation to open-source EDA tools – “How to design complex RISC-V SoC with open-source EDA tools and time to productize design ideas?”
Because India has adopted RISC-V as the national ISA, the time is now to learn from the academic luminaries who created this open architecture, and the engineers who are facilitating the mass adoption of RISC-V through customized silicon, design platforms and accelerators.
The seminar is free to attend and will include a broad spectrum of guest speakers, ranging from well-known professors at Indian institutes and research organizations to company founders and senior executives from the U.S. and India who are witnessing, first hand, the momentum of RISC-V and its impact on the worldwide semiconductor ecosystem.
All the best and happy learning…
Webinar on “SoC Reference Design of the PicoRV32 RISC-V Microprocessor” – With Kunal Ghosh, Tim Edwards & Mohamed Kassem
After successful webinar on Making of Raven Chip, this time we take the chip forward and implement using end-to-end opensource EDA tools, and all on efabless cloud. What does this mean to us? It means, you can start innovating on a design, build RTL and do synth/PD/LVS/DRC all using opensource EDA framework and not pay a single penny for license.
The big question How is this possible?
Thereby, I welcome you all to my next (follow-up) webinar with Tim Edwards and Mohamed Kassem on 2nd June and below is the
Part 1: IP digital flow and chip integration on efabless.com
- The efabless model (recap from Part 1)
- The efabless platform:
- The (updated) Marketplace
- CloudV (continued work in progress)
- Open Galaxy (updated apps)
- The Raven chip project (update)
Part 2: Digital synthesis with CloudV
- The CloudV platform
- CloudV ongoing development
- Interactive CloudV tutorial:
- Clone an open-source “soft” IP
- Synthesis using CloudV
- Export to Open Galaxy
Part 3: Synthesis flow on Open Galaxy
- Interactive tutorial:
- Clone the raven_spi IP block
- Run through “qflow” synthesis steps to layout
Part 4: Full chip integration on Open Galaxy
- Floorplanning the core
- Generating and connecting the padframe
- Placing components
- Top-level signal routing
- Top-level power routing
- Interactive tutorial: Using the layout tool for top-level integration
Tips and tricks for using the Magic VLSI layout tool efficiently
Part 5: Full-chip verification on Open Galaxy
- Additional requirements: Substrate contacts, antenna tie-downs, etc.
- Final DRC
- Final LVS
- Interactive tutorial: Using the LVS tool for top-level verification
Tips for understanding LVS errors and how to fix them
Part 6: Challenge
Design and verify a small chip in 0.18 m technology
1.8V only (no voltage regulator), applied CMOS clock (no oscillator)
- Create a simple verilog function (details TBD)
- Synthesize, place, and route the digital block
- Compose top level from padframe and digital block
- Route core to pads
- Verify DRC and LVS
Webinar “Distributed timing analysis in 100 lines code” on 26th May 2018 by Tsung-Wei Huang
Recorded Version for people who missed it !!
Webinar “RTL Synthesis QnA webinar” by Clifford Wolf and Kunal Ghosh on 19th May 2018
Our next webinar is slightly different one. It’s a Q&A webinar on RTL Synthesis, by Clifford Wolf. Clifford is architect of ‘Yosys’ which is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Clifford will be answering below 23 queries on RTL synthesis. Entry to this 2-hour webinar is FREE, recording is paid. So, buy it, if you like it.
This webinar opens 2 new opportunities, one – a chance to interact with architect of Synthesis, two – a chance to get your question in TOP25 list. Since we have already started receiving queries, make sure you draft challenging queries.
Below TOP23 query submissions are directly eligible for certificates from our company “VSD Corp. Pvt. Ltd.” All the best and happy learning.
Note of Appreciation – I have worked with Clifford in my course on TCL programming Part 1 & 2, and really Thank him for all his guidance for making of TCL programming course.
Recorded Version for people who missed it !!
We are going to present “Characterization with GUNA : A characterization tool by Paripath”. We will go through the characterization flows – flows which are popular for standard cells, memories, IP’s.
Within that, we will cover timing, noise, power and variation as 4 main topics of the characterization. Each one of those is expected to have a lab, where instructor will run GUNA as a standalone software and generate the models.
We will also clarify some concepts on chip variation, like what kind of variation exists (AOCV, POCV, SBOCV, LVF, etc), how do we tackle/model that, shortcoming of each on of this models and how do we move down the node, changing our model to account for some of the facts that show up in every transition to a new advanced node
So lot of exciting thing to be presented, and, the biggest thing about this webinar is the Instructor himself – Rohit Sharma.
Rohit Sharma is Founder and CEO of Paripath Inc based in Milpitas, CA. He graduated from IIT Delhi. He has authored 2 books and published several papers in international conferences and journals. He has contributed to electronic design automation domain for over 20 years learning, improvising and designing solutions. He is passionate about many technical topics including Machine Learning, Analysis (above image), Characterization and Modeling, which led him to architect Guna – an advanced characterization software for modern nodes. He currently works for Paripath Inc.
Date & Time : – 28th April – 9am to 1pm IST
Recorded Version for people who missed it !!
Webinar on “Machine Intelligence in EDA/CAD” on 31st March, 9 AM IST with Kunal Ghosh and Rohit Sharma
We start with Electronic design automation and what is machine learning. Then we will give overall introduction to categories of machine learning (supervised and unsupervised learning) and go about discussing that a little bit. Then we talk about the frameworks which are available today, like general purpose, big data processing and deep-learning, and which one is suitable for design automation. This is Machine Learning in general with a focus on CAD, EDA and VLSI flows.
Then we talk about Applied Theory (data sets, data analysis like data augmentation, exploratory data analysis, normalization, randomization), as to what are the terms and terminologies and what do we do with that, accuracy, how do we develop the algorithm, essentially the things that are required to develop the solution flow, let’s say, you as the company wants to add a feature in your product using machine learning, what you would be doing, and what your flow will look like and this is what is shown as pre-cursor of flight theory as what you should be looking out.
And then we start with regression, which is first in supervised learning. In the regression, we will give couple of example, like first is resistance estimation, second is polynomial regression which is capacitance estimation. For resistance estimation, we have the dataset from 20nm technology. And finally, we go on to create a linear classifier using logistic regression.
Next will be conditionality reduction, meaning, you have a large dataset and how to you reduce the size of that so that you can run on a laptop or even on your cell phone. Then there is a big example of that. Everything has mathematics behind that, this won’t be a part of the webinar.
[Follow-up webinar] Then we will move on to Deep Learning and finally we plan to have feed forward neural network, where we create couple of applications using neural networks. The first one is binary classification of cells, like you have library and we will design a neural network which can figure out a cell that’s give to it is combinational or sequential. And then, we make it broader and bring about 10 classes. So, there are 10 different type of cells (we can label them) and without giving any other information, can the neural network be designed to handle those 10 classes and can figure out which cell it is out of those 10 classes
Webinar presents a hands-on approach with session on GPUs, solving design automation problems with modern machine intelligence techniques by including step-by-step development of commercial grade applications including resistance estimation, capacitance estimation, cell classification and others using dataset extracted from designs at 20nm.
It walks the reader step by step in building solution flow for EDA problems with Python and Tensorflow.
- Design automation engineers
- Research professionals
- Graduate students
- Machine learning enthusiasts
- CAD developers, mentors
Webinar on “Making the Raven chip: How to design a RISC-V SoC”? – With Kunal Ghosh
Building a chip is like building a city…
This was the mantra with which we started our company in 2011. Now that we have covered major components of chip designing through our online courses, I think this is the right time to move from “chip designing” to “chip planning”
Chip Planning involves lot of decision making like, analog peripheral (ADC, DAC, POR, etc.), digital peripheral (UART, flash controller), memory mapping, top level connections like pad-frame, level-shifters, GPIO and many more.
Do you want to know what it is like to build a city? Enroll in webinar on 3rd March from 9am to 1pm IST with myself, Tim Edwards and Mohamed Kassem. Details of registration link will be published soon.
This is the perfect webinar for to grow and stay ahead of curve in Semiconductor and Chip design.
Webinar Description :
- .Raven SoC overview
- Run-through of Raven files:
(D) digital peripheral (UART, flash controller)
(E) memory (SRAM)
(F) analog peripheral (ADC, DAC, POR, etc.)
- Further description of SoC and choice of connections between blocks
- Memory map description
- Top-level connections: padframe, level shifters, multiplexers
- Testbench C code
- Testbench verilog code
- Make file run-through
- Running test bench series (GPIO, ADC, DAC, UART)
- Example: Create a new testbench to test bandgap voltage and use bandgap as reference to test the comparator.
- Example: Run the new test bench and verify operation.
- Overview of synthesis process
- Challenge: Add a general-purpose timer/counter module to raven_soc
(A) driven from select able sources:
(i) master clock
(ii) crystal clock
(iii) external clock
(iv) RC oscillator output
(B) 32 bits
(C) Timer output routed to GPIO or interrupt
(D) Counter output memory mapped
(E) Control values are the amount to add to the counter per clock cycle and the value at which to toggle the timer output.
(F) One-shot or continuous
(G) Continuous mode may restart at zero or wrap around.
Recorded Version for people who missed it !!
Pipelining RISC-V with Transaction-Level Verilog Webinar on 10th Feb 2018
Pipeline implementation – Which one is better? And Why?
Have you implemented a processor using Verilog? Which was the most important part of your implementation? What was your code size in Verilog? What if, we told you that you can reduce your verilog code size by about 3.5x by a new technology? What if, we told you that you can create any digital sequential logic you can dream up faster than you ever thought possible, all within your browser, probably Google Chrome?How about a ‘change’? Change the way you used to write your verilog code. Change the way you used to implement Pipelining for your processor. Change is the only “constant”Did this blog make you think? I encourage and welcome you to think in the right direction with experts from this field in my next webinar on “Pipelining RISC-V with Transaction-Level Verilog” on 10th Feb’ 2018. Just like my any previous webinars, even in this one, you will be able to interact with industry experts directlyAnd this time, we have instructors all the way from Greater Boston Area, US, with more than 18+ years of experience in the field of “Logic Design and Verification”All I can say is, me and participants who will be attending this webinar, will be “blessed”. I would re-iterate, just like my previous webinar emails, “recording is good, but LIVE is best”Stay tuned for tickets link and more about this webinar!!!Happy Learning…
Recorded version of Webinar who missed LIVE !!
Physical design webinar – 20th Jan – With Kunal Ghosh
What if I told you, you can design chip without installing any tools on your laptop?What if I told you, you can design chip on cloud, just like Amazon eFPGA?What if I told you, you can design chip for FREE?Don’t believe it…Well, attend my first physical design webinar on 20th Jan, and stay tuned to below link for more updates:This will be first ever webinar, where we will bring in industry EDA expert and EDA tool architect as support, while myself driving the webinarLearning something new is always good, as this might just what will happen in few years from now. (Amazon eFPGA – where you can setup FPGA environment on cloud and run your simulations – has proven that). Something similar will happen for back-end physical designThis year, we will begin with something new in the field of chip design, and let this webinar be the start…Like my all other webinars, expect a humongous discussion and interaction with experts.
Recorded version of Webinar who missed LIVE !!
Timing ECO webinar on 6th Jan…. Lets produce better chips
First, lets define better? Better in terms of Power. Performance and AreaEvery VLSI engineer, an RTL architect, or Lead Synthesis Engineer, or Senior Physical Designer, or Director of Signoff timing analysis practically everyone is doing timing ECO at every step of their flow. I, being a part of Signoff timing analysis and Physical Design world, am doing ECO almost every day, and so I understood that its more than adding buffer and upsizing/downsizing cells.All the factors or ways shown in above image impacts either dynamic power or short-circuit power or leakage power. The question is, do you know why do we still do it? Do you know how can we still do with minimally impact on other parameters? Yes, No, Dont Know.Its time to unveil more than 15 strategies to do timing ECO and below are few of them
- Routing congestion aware timing ECO
- Path based analysis ECO for selected endpoints
- Replicated modules based timing ECO
- Legalized timing ECO
- Margin based timing ECO
.and many moreSee, I told you, timing ECO is more than just adding buffers and sizing cells.Do you want to know all the strategies? Do you want to be a better timing engineer? Engineering includes tons of changes and modifications from inception to final product. Hence its called Engineering Change Order (ECO)Join the webinar on Jan 6th 9am to 12pm IST. Inviting students and professionals from India, US, Egypt, UK, and all over the world
Recorded version of Webinar for people who missed LIVE !!
How open source will begin innovation? STA Webinar :-Analyze your chip timing for FREE
Recorded version of the Webinar for people who missed LIVE !!https://youtu.be/0dffOwNQdBg
STATIC TIMING ANALYSIS (STA) WORKSHOP
Let’s begin with Second expert workshop in STA, after completing a full energy packed first workshop filled with freshers, professionals and also expertise in the field.VSD workshops are community events, where like-minded individuals get together, learn, practice and share ideas on what it take to build a design using open source EDA tools, also how to develop productive work culture with highly engaged designers.Following a knowledge ice-breaker and an innovative designing using open source tools, Lets have some more practice session to build a structure and to represent how an energetic community work towards developing a great CHIP DESIGN !!
Open-source EDA community building using technology-mediated learning
Kunal will talk about a novel technique of building open-source hardware community using adaptive and adaptable learning mode with open-source EDA tools. The gap confronted here is shortfall of guidelines and support systems to use these tools, and one architecture that connects complete design to all tools. VSD has been attempting to fill this gap by blending the learning and practicing methods through online video courses with the goal of building a large community across the globe who are designing and innovating using open-source tools.