JOIN VSDOpen2020 and be a part of open-source revolution !!

VSDOpen 2020 is bigger and better !!
VSDOpen 2020 has LIVE Tutorial Session for first 3 days
VSDOpen 2020 will showcase open-source analog IP’s
VSDOpen 2020 is for 4-days

We are really excited to showcase some masterpieces of work done by Research Interns over last year, and also, we are really excited to introduce you to novel techniques of learning and designing analog/digital IP’s. This time, we are about to showcase you a list of projects which was achieved for the very first time in the field of open-source.

To Begin with: First time in the open-source world, 
  • We have open-source analog IP’s built from scratch using OSU-180nm PDK, Magic and eSim EDA tools, by undergrad and postgrad students. Unbelievable!!
  • We displayed to the RISC-V community around the globe how you can design a basic RISC-V core in just 5-days from scratch using TL-Verilog and Makerchip IDE. Unbelievable!!
  • We released a cloud-based VSD-Intelligent Assessment Technology platform which enables VLSI training for all time-zones at one go and is about 99% effective compared to any other training around the globe.
  • We will show you how you can develop your own SoC using real 130nm PDK from Skywater and OpenLANE EDAtool-chain from efabless

VSDOpen 2020 Distinguished Speaker

Conference Date

VSDOpen 2020 Cloud Lab based Workshop

On VSD-IAT Platform (Access open for 24 Hrs)

Date

Workshop Title

Instructor 

Registration Fees

7th October 2020

Open Source EDA Tool Development

Tim Edwards

$5

8th October 2020

RISC-V Microarchitecture TL-Verilog

Steve Hoover

$5

9th October 2020

SoC Design using OpenLane

Mohammed Shalan

$5

7-9 October 2020

Register for all 3 Workshop

$15   $10

International Participant
Indian Participant

VSDOpen 2020 Open Source IP Designer track

Title

Speaker

University/Organisation

SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns (OpenRAM)

Yash Kumar

Fr. Conceicao Rodrigues College of Engineering, Mumbai University

10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

Ashutosh Sharma

Indian Institute of Information Technology Design and Manufacturing, Kurnool

On-chip Clock multiplier (pll) (Fclkin – 5MHz to 12Mhz, Fclkout – 40MHz to 100MHz at 1.8v

Paras Sanjay Gidd

Manipal Institute of Technology, Manipal, Mangalore

10 bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

Sheryl Serrao
Ananya Ghorai
Shalini Priya
Uday Vempalli

Fr. Conceicao Rodrigues College of Engineering, Mumbai University

IIT(ISM), Dhanbad
NIT, Jamshedpur

Siddhartha Institute of engineering and technology, Puttur, A. P

Next Gen open-source VLSI/RISC-V trainings using VSD-IAT, Makerchip and TL-Verilog

Shivani Shah

International Institute of Information Technology, Bangalore

VSDOpen 2020 Conference Schedule

Time (IST)

Session

Talk Title

Speaker

Organisation/University

08:00-08:15

VSDOpen 2020 Inauguration

Inception of Online Conference

Kunal Ghosh

VSD

08:15-08:45

Keynote

Applying Community Models to ICs: Why and How

Michael Wishart

Efabless

08:45-09:05

Open Source IP Designer track

SRAM (1024 x 32): (32kbits or 4kB), 1.8V and access time is <2.5ns (OpenRAM)

Yash Kumar

Fr. Conceicao Rodrigues College of Engineering, Mumbai University

09:05-09:25

Open Source IP Designer track

Next Gen open-source VLSI/RISC-V trainings using VSD-IAT, Makerchip and TL-Verilog

Shivani Shah

International Institute of Information Technology, Bangalore

09:30-10:00

Keynote

RISC-V and open source hardware – A golden opportunity for India semiconductor industry

Naveed Sherwani

SiFive

10:20-10:40

Open Source IP Designer track

10bit potentiometric DAC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

Ashutosh Sharma

Indian Institute of Information Technology Design and Manufacturing, Kurnool

11:00-11:15

Open Source IP Designer track

On-chip Clock multiplier (pll) (Fclkin – 5MHz to 12Mhz, Fclkout – 40MHz to 100MHz at 1.8v

Paras Sanjay Gidd

Manipal Institute of Technology, Manipal, Mangalore

11:00-11:15

Networking Break

Forum is open for all

Community


11:15-11:45

Keynote

Computation in the Post-Moore Era: Reflecting on the The role of Open Source

Jan Rabey

Berkeley University

11:45-12:15

Industry Talk

A brief history of open hardware: learning from the freeand open source software movement

Jeremy Bennett

Embecosm

12:15-12:45

Open Source IP Designer track

10 bit ADC 3.3v analog voltage, 1.8v digital voltage and 1 off-chip external voltage reference

Sheryl Serrao, Ananya Ghorai, Shalini Priya, Uday Vempalli

FRCIT Mumbai, IIT(ISM)Dhanbad, NIT Jamshedpur,SIET Puttur, IIIT Bangalore

12:45-13:15

Talk by Govt. of India

Government Initiatives in ESDM Space

Sunita Verma

Meity, Govt. Of India

13:15-13:45

VSDOpen Closing

Future path of Open source and VSD

Anagha & Kunal

VSD

13:45-14:00

Networking

Forum is open for all

Community

In Collaboration with: