Workshop Day wise Content :

Day 1 : Introduction to RISC-V ISA and GNU compiler toolchain

  1. Introduction to RISC-V basic keywords
  2. Labwork for RISC-V software toolchain
  3. Integer number representation
  4. Signed and unsigned arithmetic operations
Day 2: Introduction to ABI and basic verification flow
  1. Application Binary interface (ABI)
  2. Lab work using ABI function calls
  3. Basic verification flow using iverilog

Day 3: Digital Logic with TL-Verilog and Makerchip

  1. Combinational logic in TL-Verilog using Makerchip
  2. Sequential and pipelined logic
  3. Validity
  4. Hierarchy

Day 4: Basic RISC-V CPU micro-architecture

  1. Microarchitecture and testbench for a simple RISC-V CPU
  2. Fetch, decode, and execute logic
  3. RISC-V control logic

Day 5: Complete Pipelined RISC-V CPU micro-architecture/store

  1. Pipelining the CPU
  2. Load and store instructions and memory
  3. Completing the RISC-V CPU
  4. Wrap-up and future opportunities

Instructor Profile:

Kunal Ghosh, co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd., Kunal pioneers in the field of online open-source EDA (qflow & openroad)/open-source hardware (specially RISC-V) design and learning. Currently, Kunal owns around 32 high-quality VLSI online courses in and around open-source EDA/hardware, which is being consumed by around 28700+ students around 141 countries. Apart from trainings, Kunal has also worked with IIT Madras and IIT Guwahati on open-source activities and design projects. Currently, Kunal and his team are working on developing high quality open-source Analog/Digital IP’s which would be first one’s in the field of open-source hardware design. Prior to VSD, Kunal has worked with Qualcomm and Cadence, in field of SoC design. Kunal has done his Masters at IIT Bombay in field of VLSI & Nano-electronics, with specialisation in Sub-100nm Electron Beam Lithography Optimisation techniques

Steve Hoover, founder of Redwood EDA, Steve is fostering an open-source silicon ecosystem through numerous technologies including the WARP-V CPU core generator with support for RISC-V. His main focus is design methodology and tools enabled by Transaction-Level Verilog (TL-Verilog), available to all at He is also the lead developer of the 1st CLaaS open-source framework for cloud FPGAs. Steve holds a BS in electrical engineering summa cum laude from Rensselaer Polytechnic Institute and an MS in computer science from the University of Illinois. He has designed numerous components for high-performance server CPUs and network architectures for DEC, Compaq, and Intel.



For details Email :

Anagha Ghosh (