Why is a Physical Design workshop important for education?

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Hi Kunal

Traditional pieces of training have taken an orthogonal shift, post-release of open-source EDA tools and SKY130 foundry. This has brought a huge opportunity for semiconductor ed-tech companies like VSD to close a wide gap within many training companies that have shifted their curriculum from theoretical PDK to real PDK. If you are a student, who is reading this email, do not panic if you are not aware of PDK. This is something which we are covering in the workshop.

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Random Verification in Hardware – A Primer

Join us to explore such concepts and more, where we use Python to leverage its library-rich environment feasible for verification using Vyoma’s UpTickPro platform, in this edition of Capture the Bug hackathon, organized by NIELIT, Calicut, mentored by IIT Madras, in association with VLSI System Design and Vyoma Systems.
Hackathon details – https://nielithackathon.in/

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Successful VSD hackathon mantra – Trust, plan and execute !!

To provide a basic hands-on for design verification, which enhances practical verification knowledge. The verification challenge helps to understand the verification intent to detect bugs in designs, understand debugging and fix the buggy designs. It provides a practical exposure to real world design verification activities

The hackathon aims to generate skilled manpower in the domain of Design Verification, which will strengthen the quality of designs being manufactured. It reduces chip failure, improving the time to market cycle of Semiconductor products.

The Indian government initiative Chips to Startup (C2S) programme aims to propel innovation, build domestic capacities to ensure hardware sovereignty, and build a semiconductor ecosystem that requires 85,000+ highly trained engineers. Working towards this vision statement, we have planned the 3-Week “Capture the Bug” , a Design Verification Challenge.
This Hackathon is organized by NIELIT Calicut and technically facilitated by Vyoma Systems , VLSI System Design & IEEE Robotics and Automation Society and ably mentored by Indian Institute of Technology Madras (IIT Madras).

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VSD-HDP : Verilator Verification Environment for RISC-V vector accelerator

In a nutshell, the project really is to build a Verilator Verification environment i.e. a structure in which we can set up testbenches that are executed with Verilator. The thing which is interesting in this project is we are going to tie that Verilator piece with a golden model arithmetic library and that is going to be something that you can publish as nobody else in the world has that

It’s a Verilator Testbench environment that uses an online arithmetic library to generate the right bit pattern. We are not using randoms, but we are using a Golden model. If you progress from ALU to a vector accelerator, you will have a vector lane, vector register file, vector load/store unit, vector instructions.

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What I did in 8-weeks-VSD Internship? – Vezzal

Constant development of tools often breaks something internally which can lead to other issues. Hence there is a need to test the tool for its previous supporting features. But the tool needs an environment to get launched and good test cases to test the features. This is called as “Continuous Integration (CI)”. I

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