VSD Summer Internship – VLSI System Design

Embedded and Chip design Education curriculum – All in one via VSDSquadron

The VSDSquadron educational board provides a unique opportunity for learners to gain hands-on experience in electronics system design and chip design. The board’s open-source nature allows for easy access to IPs, PDKs, and tools, including RISC-V, providing learners with a complete and comprehensive curriculum in these areas. With the board’s built-in modules covering a range of topics such as analog IP design, RISC-V SoC design, PCB design, and more, learners can acquire practical skills and knowledge essential for a career in the field. In summary, the VSDSquadron educational board offers a rich and dynamic learning experience in electronics system design and chip design.
International payments are now open. You can pre-order your board using below link
https://www.vlsisystemdesign.com/vsdsquadron/

Successful VSD hackathon mantra – Trust, plan and execute !!

To provide a basic hands-on for design verification, which enhances practical verification knowledge. The verification challenge helps to understand the verification intent to detect bugs in designs, understand debugging and fix the buggy designs. It provides a practical exposure to real world design verification activities

The hackathon aims to generate skilled manpower in the domain of Design Verification, which will strengthen the quality of designs being manufactured. It reduces chip failure, improving the time to market cycle of Semiconductor products.

The Indian government initiative Chips to Startup (C2S) programme aims to propel innovation, build domestic capacities to ensure hardware sovereignty, and build a semiconductor ecosystem that requires 85,000+ highly trained engineers. Working towards this vision statement, we have planned the 3-Week “Capture the Bug” , a Design Verification Challenge.
This Hackathon is organized by NIELIT Calicut and technically facilitated by Vyoma Systems , VLSI System Design & IEEE Robotics and Automation Society and ably mentored by Indian Institute of Technology Madras (IIT Madras).

What I did in 8-weeks-VSD Internship? – Vezzal

Constant development of tools often breaks something internally which can lead to other issues. Hence there is a need to test the tool for its previous supporting features. But the tool needs an environment to get launched and good test cases to test the features. This is called as “Continuous Integration (CI)”. I

VSD delivered 1st online analog tapeout workshop using Sky130

VSD promises to deliver similar IP design workshops in upcoming days, followed by the next big leap – SoC design workshop with VSD SoC generator using all VSD IPs developed by VSD community using Skywater 130 nm technology node.

VSD aims to tackle global chip designer shortage

Above article does talk about chip shortage, which is due to increased demand of consumer electronics like laptops, tablets, mobiles, which was never the case […]

Ever heard of Chip Design Pentagon?

Know what Pentagon is? It is a plane figure which has 5-straight sides and 5-angles. For a perfect pentagon, it needs all its sides and angles to be the same, till the last decimal. Do you know what is the similarity between pentagon and our upcoming workshop “Advanced Physical Design workshop using OpenLANE/SKY130”? Look above image and you would guess it right. It is a perfect blend of topics where even a fresher can jump-start his/her career in chip design in just 5-days

7th mile-stone in open-source analog IP design – 10-bit DAC

Ashutosh had joined our VSD Research IP design internship group 8-weeks back, along with 30 other interns. His journey on was from “I can’t, its too difficult” to “I did it”. Personally, only I know how hard it was for him when he saw an industry grade 10-bit DAC specifications on VSD IP website. We managed to achieve post-layout DNL of 3.5LSB and INL of 3.7LSB, which as per experience, is really tough for a fresher to achieve in a span of 8-weeks, but not impossible.

6th mile-stone in field of open-source – FREE VLSI tool installation course

A full-fledged video lectures on step-by-step process to install OpenLANE EDA tool chain and Sky130 PDK open-process on your own laptop, from scratch. There is a dependency on vsdflow, though for fresh users and with Windows or fresh Unix machines. To do something like this, it needs a clear focus on end vision, with very good VLSI fundamentals, which demands hours of efforts every day

3rd mile-stone in 1-week in field of open-source – 4kB SRAM design

@Yash joined our research project group under VSD Research internship program which runs for 8-weeks. He was supposed to explore openRAM memory compiler flow, develop all custom cells required by openRAM using OSU180nm and generate 4kB SRAM with an access time of 2.5ns