Machine Intelligence webinar overview

Webinar presents a hands-on approach with session on GPUs, solving design automation problems with modern machine intelligence techniques by including step-by-step development of commercial grade applications including resistance estimation, capacitance estimation, cell classification and others using dataset extracted from designs at 20nm.

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The beauty of slack-based timing ECO

A timing ECO should be power, performance and area aware and that was the crux of this webinar, where we discussed several strategies about how to do effective ECO as an expert .Slack based ECO is a beautiful strategy which helps you to achieve your timing target, while helping you to reduce on power and area

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From VLSI to System Design (SoC) – The choice of SPI

SPI model is a master/slave model. There’s some SPI master which determines who gets to transmit and who gets to receive. The output from SPI master is called MOSI (Master Out Slave In). If you have 2 slaves, slave 1 and slave 2, as shown below, MOSI goes to all the slaves .Then you have another line MISO (Master In Slave Out). All the wires are connected, as shown in below image. Then you have a master only function called SCLK, which goes to all the slaves. Now also, there must be a slave select (SS) for S1 and a slave select for S2.

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– 没有你的支持,这是不可能的

our company to move from LMS (Learning Management System) to EMS (EDA Management System), and finally we envision, very soon to be in DMS (Design Management System).Talking about ‘vsdflow’, it’s the main theme of this paper, and if I had to describe it in few lines, it’s a ‘plug and play (PnP)’ EDA management system, built for chip designers to implement their ideas and convert to GDSII.

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PPA (power, performance, area) card

A PPA card like the above, is something which every VLSI engineer should be carrying like a business card. Why? Right from RTL to synthesis to PNR to signoff, we do things like upsize, downsize, VT swap, and many more, and all these factors impacts or tweaks your design PPA in one way or the other.
Let’s take an example of ‘downsize’

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Committed in 2011, delivered in 2018

the flowchart is what you need to understand just to be an expert in the field of VLSI and semiconductors. Every topic shown in above image is a field, and every topic has a beautiful physics behind it, which when blended with tools in a video course, becomes a master-piece

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The Perfect Launch – By Kunal and Rajeev

We launched industry grade PNR EDA tool ‘Proton’ on web in front of 100 people across 7 countries, which I think, by far, has been a perfect launch for any partial open-source EDA tool.The below link has the details of the launch:
https://www.udemy.com/vsd-physical-design-webinar-using-eda-tool-proton/

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Facts – About below open-source EDA tool

Why “integrated”? Because at lower nodes, you have to integrate other parts of the flow. Sign-off (you can see power and timing buttons below), clock tree synthesis (you can see synthesis button) must be integrated, so we have a fully integrated PnR flow that we built from day one.

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