Timing-driven optimization is imperative for the success of closure flows. The optimization engine applies changes to the design and estimates circuit delays quickly and accurately to improve timing, area, and power performance. This procedure is inherently complex and computationally challenging.
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VSDOpen 2018 Keynote 1 : A New Golden Age for Computer Architecture: History, Challenges, and Opportunities
A New Golden Age for Computer Architecture: History, Challenges, and Opportunities, David Patterson, UC Berkeley and Google, October 26, 2018Full Turing Lecture: https://www.acm.org/hennessy-patterson-turing-lecture
Welcome to first ever online semiconductor technology conference with prime focus to build SoC using RISC-V CPU using Open-source EDA tool on 27th October 2018, 8:00 AM to 3:00 PM
Free registration for IITM Participants:
Online viewing Zoom link will be send 12 hours in advance.
Alternatively, IITM view point: A.M. Turing Hall (BSB 361)
Please register using the form below, its on first come first serve basis.
Contact us at 8548037643 or firstname.lastname@example.org
Design Verification is critical to proving functional correctness and establishing confidence in a design. Several studies from industry and academia, particularly over the course of the last two decades, have explored various verification methodologies that fall somewhere between dynamic or purely static formal approaches.
Random stimulus methods perform better because they eventually cover many cases. Most new ideas in dynamic verification over the last two decades have largely been towards semi formal verification methodologies such as coverage driven verification and constrained test generation. In this paper, we explore an approach to dynamic functional verification that we use at the RISE lab, IIT Madras for the verification of the RISC-V based Shakti cores.
This paper describes an opensource padframe generator that was developed on the efabless platform for usage with the Open-Source Qflow Digital Synthesis Flow, for digital logic chips in the X-FAB XH018, 180nm process. It is presented by Philipp, who is a software developer with a strong background in security and cryptography. He is currently learning microelectronics.
“Rapid Physical IC Implementation and Integration using Efabless Platform”. This paper describe a rapid backend process flow (synthesis, placement, STA, routing) and top level integration to implement a small RTL IP into a tapeout ready chip using the Efabless online platform
AI and machine learning (branch of AI) needs deep neural networks, which in turn requires high-performance computing. SiFive and RISC-V organization were happy to announce a solution, tailored to this requirement to AI/ML start-ups in Bangalore on 23rd August
The tech symposium started with Krste’s talk on “History of RISC-V Ecosystem around the world”. The talk started from very basic topic like “Why Instruction Set Architecture Matters?” and ended on a very important note on the need of a FREE ISA. He also provided ideas on how chip design factories can become company like Instagram, which exactly is everybody’s vision of abstracting details, and take advantage of existing online infrastructure
We would like to invite you to attend one of the SiFive & Open-Silicon Tech Symposiums taking place at six different locations throughout India in August. See map in below image for exact locations and date of events.
I would be presenting a very important tutorial, which closely connects open-source ISA implementation to open-source EDA tools – “How to design complex RISC-V SoC with open-source EDA tools and time to productize design ideas?”