Hey There, This is rather a very curious query I had, when I was learning Magic VLSI Layout tool, and I am very sure, every […]

Hey There, Now that it’s clear, that we can tapeout using open-source EDA tools (referring to recent RavenSoC tapeout by Efabless Corp. Pvt. Ltd. using […]

Hey There, Last week, I consulted around 20 colleges to install ‘vsdflow’ on their Linux Ubuntu and CentOS machines. There were many successful installations and […]

to build the shell script for ‘vsdflow’ on CentOS, and finally I have the first cut ready. You just need to follow steps given in below link for CentOS, and all opensource EDA tools (PNR, STA, Layout, LVS) will be installed on your system. There are 2 testcases (picorv32 and spi_slave) inside the below link to test whether all tools have been installed or not. After running the shell script in below link, you need run the testcase

So, I took up two STA tools, OpenSTA from openroad project and “——-” from “——-“, to explain, to some extent, what “bench-marking” means to me. I would also encourage everyone reading this blog to come up with their definitions of “bench-marks” for other tools and we can model that. You can fill-up “——” with one of your favorite industry grade EDA tools. The concept of benchmark won’t change

Power rail discontinuity – We would like to have continuous power rail.N- and P-diffusion discontinuity – We would like to have continuous diffusion. For my Physical design friends, remember, we add “FILLER” cells at the end of routing, and you always wondered why we are doing so.Small substrate contacts – Except for inverter, all substrate contacts are single width, which will create high resistance path for current, thus increasing “Clk-to-Q” delay.Hanging metal1 – If you see for the NAND gate outputs, there is lot of hanging metal1.

Hey There, Of-course there is a requirement for open-source verification, but that’s not the only thing we want to cater to. There are other verification […]

Hey There – Think about it…!! Problem Statement – For hierarchical designs ~500k instance count, participants are expected to develop code which will modify existing […]

For hierarchical designs ~500k instance count, participants are expected to develop code which will build clock tree for a design which has close to ~50k sequential flip-flops using default routing rules