DRC is something which (most likely) is supposed to fail in first instance. Let’s see what you do to fix them. In below eg. drc count is 25. Qrouter (an open-source router, which will be discussed in detail in webinar) is really good with some standard cell sets like the one which comes distributed with qflow, like OSU018, they are really nice one’s to work with. All the ports have nice squares, they don’t have these inside ‘L’ corners as shown below.
A working chip is all using opensource EDA tools (no more license fee). Of course, its taped-out in 180nm technology. But who knows, this might be just the beginning. Upcoming blogs will talk more about the commercial angle of this. Let’s see how it is going to benefit student/professionals/innovators community
Do you want to find your answers too? Enroll in the upcoming webinar on “Distributed timing analysis” with Tsung-Wei, do labs on your own, understand the framework and I can guarantee you would be a better STA engineer or Lead than you were before 26th May.
There are multiple places, we can introduce distributed computing to timing and major motivation is to speed up the timing closure. We have to analyze timing under different range of conditions, typically quantified as modes (test mode, functional mode) and corner (PVT). The number of combinations (timing views) you have to run is typically increasing exponentially with lower nodes. That’s where you need to need to distribute timing analysis across different machines.
Just to give you some background, picoSoC is an example SoC using PicoRV32, and PicoRV32 is a size-optimized RISC-V CPU which implements RV32IMC instruction set architecture.
Last week we conducted Machine Learning contest where participants were asked to modify loss function program to bring out best possible accuracy in terms of mean and sigma, by designing a new multinomial model. We have a winner and a special mention
The above waterfall diagram is representing a sequence of instructions that are fetched from memory and how they progress to the various stages of pipeline. In the above diagram you got program counter (P), fetch (F), decode (D), register read (R), execute (E) and register write (W). We fetch one instruction at a time. Potentially, you can fetch multiple instructions at a time, which would be a super-scalar architecture.
If you learn this tool and use it to build your own applications, you might end up presenting a paper in our online conference happening soon called “VSDOpen” – The first ever online conference on opensource EDA.
Well, that’s was just a demo of the powerful efabless platform. Do you want to know more about this powerful yet simple platform? Do you want to build complete SoC using this platform? We did an entire webinar on this, and here’s the copy of it.
let’s identify what has happened till date in field of EDA/CAD using Machine intelligence. The image below shows the flow diagram for designing a chip. This is what has happened (or happening) in EDA using machine intelligence.