So glad and happy to let you know that we will be presenting in RISC-V workshop at IIT Madras, India, on July 19, 2018 at 2pm (organized by RISC-V foundation), and topic is something which we have mastered in last 7 years – its about a survey of E31 RISC-V core floorplan and its impact on power, performance and area.
That’s exactly what happened in DAC2018 at Moscone Center, San Francisco. I was invited for a talk in DAC summer school, on my work “vsdflow” which is also one of the main topics of discussion in my “TCL programming” course on Udemy. I would say, the entire DAC was a journey of events, exchange of ideas between brightest minds of the world.
A good takeaway from above is which is the best flow – Well, there is no single answer to this. You can use “flow 1”, if your organization is constrained by cost and comparable performance, and you can go for “flow 2” if performance is the criteria.
Symposium VI – Standard cell layout/characterization, ECSM puts its number in the same arc as NLDM. The numbers you see in above image, below the cell_rise, cell_fall, rise_transition is all NLDM information. Under rise_transition, you will have ecsm_waveform and ecsm_capacitance. Now this is only one waveform, because we gave it only one load and one slope, just like we have one value under “rise_transition”. If we had 3×3 under rise_transition, then you would have had ecsm_waveform(“0”), ecsm_waveform(“1”), till ecsm_waveform(“8”), essentially 9 waveforms. And same thing with capacitance
Symposium V – Machine Intelligence in EDA/CAD applications- Let’s investigate a simple Wire Resistance Estimate (WiRE) model
This is common design automation problem which is used for estimating timing and power characteristics for analysis and implementation for many steps in ASIC flow. We will restrict our scope to physical implementation only, where known quantity is “length” of wire and resistance is predicted.
Question – Who doesn’t want a 3.5X improvement in their code size? I guess everyone wants efficient and effective improvement. Now these are just few tips to have the easy implementation of pipe-line. You are free to implement your ideas in TL-verilog, compile, simulate and see the improvements on your own. For few more tips, you might want to check out below course on “VSD – Pipelining RISC-
V with TL-verilog”
A new company marked its presence in market amidst Intel, Purdue university, and other top industries in DAC 2018 (see below image). It took exactly […]
This blog is regarding abstract submission for VSDOpen2018, which is the first online conference in VLSI, that covers all aspects of semiconductor technology with prime focus to build SoC using RISC-V CPU by illustrating exciting ways using (only) opensource EDA tools.
A proud moment for our company VLSI System Design Corporation Pvt. Ltd., for my colleague Anagha Ghosh and for myself (See image below)
Our company’s first paper on IEEE explore for technology mediated learning – World’s prestigious institute for engineering and technology innovation. Here’s the link for the paper
DRC is something which (most likely) is supposed to fail in first instance. Let’s see what you do to fix them. In below eg. drc count is 25. Qrouter (an open-source router, which will be discussed in detail in webinar) is really good with some standard cell sets like the one which comes distributed with qflow, like OSU018, they are really nice one’s to work with. All the ports have nice squares, they don’t have these inside ‘L’ corners as shown below.