Foundry IP’s vs Macros – 10years to solve this query

A great one – not only for VSD, but also for entire VSD community. The journey has just begun, in nutshell, below image shows a well-designed VLSI Skilling model (VSD Workshops + VSD-IP design Internship + Tapeout[working on it]), which is not just participants driven but also silicon proven. To summarize, given a problem statement, VSD Interns and participants, who have gone through this rigorous training and designing model will have much better ways to figure out solutions by themselves.

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150+ students have decided to upskill in VLSI

And that’s where VSD must play an especially important role to bring in latest and greatest VLSI skills to you, atleast in the field of open-source hardware. VSD owes a lot to VLSI community and hence has planned 3 exclusive cloud lab-based VLSI workshops on 3 important topics, with top 3 expert instructors from around globe,  having more than 2 decades of experience – Tim Edwards, Steve Hoover, and Prof. Mohamed Shalan

Open-source EDA tool development with lab exercises using Sky130 pdk’s by Google/Skywater
RISC-V micro-architecture using transaction level – Verilog with lab exercises on Makerchip Platform
SoC and Physical Design using Automated RTL2GDS OpenLANE tool with lab exercises using demo design and Sky130 pdk’s.

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India’s ESDM and World’s open-source vision

All the people whom you see in below image were a part of VSD 8-week Research IP design internship program, all interns are from colleges in India, and all of them built some cool analog IP’s from scratch. This internship program partially and unknowingly executes India’s ESDM vision and World’s open-source vision, all by college students, who passionately worked close to 14-15hours per day

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7th mile-stone in open-source analog IP design – 10-bit DAC

Ashutosh had joined our VSD Research IP design internship group 8-weeks back, along with 30 other interns. His journey on was from “I can’t, its too difficult” to “I did it”. Personally, only I know how hard it was for him when he saw an industry grade 10-bit DAC specifications on VSD IP website. We managed to achieve post-layout DNL of 3.5LSB and INL of 3.7LSB, which as per experience, is really tough for a fresher to achieve in a span of 8-weeks, but not impossible.

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6th mile-stone in field of open-source – FREE VLSI tool installation course

A full-fledged video lectures on step-by-step process to install OpenLANE EDA tool chain and Sky130 PDK open-process on your own laptop, from scratch. There is a dependency on vsdflow, though for fresh users and with Windows or fresh Unix machines. To do something like this, it needs a clear focus on end vision, with very good VLSI fundamentals, which demands hours of efforts every day

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2nd mile-stone in field open-source (open-lane EDA + Google/Sky130)

@Nickson joined our research project group under VSD Research internship program which runs for 8-weeks. He was supposed to develop flow for standard cell design and characterization using all open-source tools – magic/ngspice, then plug those standard cells into open-source PNR flow by open-lane, and benchmark RTL2GDS flow results. This needed a knowledge, not only of PNR, but device physics, custom layout, DRC/LVS and then (finally) Physical design/STA.

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