From concept to algorithm – RISC-V floating point addition

First thing which comes in the title is “concept”, which is the simple one. It says, if I want to add 2 floating-point numbers, I simply add them. Second, “algorithm” is the details for a computer, how it will add 2 floating-point numbers.Third, which is “RISC-V”, which deals with binary numbers, describes how can you use same concept and algorithm to do a “binary floating-point addition”

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RISC-V Workshop @IIT Madras – Day 1

A keynote from Rick O’ Connor, executive director, RISC-V foundation, and we remember this to core of our heart, because of the below statement he made – “RISC-v is present in 27 countries and can be used by 57 % of population of World soon” That’s the spread of open-source ISA

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A tribute to opensource (EDA and ISA)

Since then, we have promoted courses using a lot of open-source EDA tools like Opentimer for STA, qflow for Physical design, TL-verilog for pipelining, Yosys for Synthesis, Proton for EDA and many more. Not only that, we have organized an online conference (as you might be aware) and here’s the link with details:

https://www.vlsisystemdesign.com/vsdopen2018-2/

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Inception of “bias” in IEEE754 floating point standard

how the IEEE754 floating point standard designed the way it is. Every great design begins with an even better story. We all must have read blogs and watched videos about how to convert a decimal floating-point number to its binary form. We must have seen standard formulas of converting an IEEE754 standard floating-point number to its decimal form.

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Chennai, we are coming to you for next RISC-V workshop…

So glad and happy to let you know that we will be presenting in RISC-V workshop at IIT Madras, India, on July 19, 2018 at 2pm (organized by RISC-V foundation), and topic is something which we have mastered in last 7 years – its about a survey of E31 RISC-V core floorplan and its impact on power, performance and area.

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An overview of Design Automation Conference (DAC) 2018

That’s exactly what happened in DAC2018 at Moscone Center, San Francisco. I was invited for a talk in DAC summer school, on my work “vsdflow” which is also one of the main topics of discussion in my “TCL programming” course on Udemy. I would say, the entire DAC was a journey of events, exchange of ideas between brightest minds of the world.

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Symposium VI – Standard cell layout/characterization

Symposium VI – Standard cell layout/characterization, ECSM puts its number in the same arc as NLDM. The numbers you see in above image, below the cell_rise, cell_fall, rise_transition is all NLDM information. Under rise_transition, you will have ecsm_waveform and ecsm_capacitance. Now this is only one waveform, because we gave it only one load and one slope, just like we have one value under “rise_transition”. If we had 3×3 under rise_transition, then you would have had ecsm_waveform(“0”), ecsm_waveform(“1”), till ecsm_waveform(“8”), essentially 9 waveforms. And same thing with capacitance

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