eFabless is back…with synth/PD/DRC/LVS…and a working CHIP

A working chip is all using opensource EDA tools (no more license fee). Of course, its taped-out in 180nm technology. But who knows, this might be just the beginning. Upcoming blogs will talk more about the commercial angle of this. Let’s see how it is going to benefit student/professionals/innovators community

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Distributed timing analysis webinar

There are multiple places, we can introduce distributed computing to timing and major motivation is to speed up the timing closure. We have to analyze timing under different range of conditions, typically quantified as modes (test mode, functional mode) and corner (PVT). The number of combinations (timing views) you have to run is typically increasing exponentially with lower nodes. That’s where you need to need to distribute timing analysis across different machines.

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RISC-V waterfall diagram and hazards

The above waterfall diagram is representing a sequence of instructions that are fetched from memory and how they progress to the various stages of pipeline. In the above diagram you got program counter (P), fetch (F), decode (D), register read (R), execute (E) and register write (W). We fetch one instruction at a time. Potentially, you can fetch multiple instructions at a time, which would be a super-scalar architecture.

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Use this tool for PNR – Its FREE

If you learn this tool and use it to build your own applications, you might end up presenting a paper in our online conference happening soon called “VSDOpen” – The first ever online conference on opensource EDA.

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