read_sdc – clock constraints

read_sdc is been considered as a very critical command in EDA world, as this is the command which defines your specifications, and if not written and interpreted correctly, can lead a huge delay in tapeout cycle.

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meet our technology partners

Hi Glad to have a prestigious institution (University of Illinois) and a market leader in Library characterization/modelling (Paripath) as our technology partners. For more, read […]

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About me….

Never really found a chance to properly introduce myself and my background to all of you. So here it is… My name is Kunal Ghosh […]

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