Blogs – Page 12 – VLSI System Design

Coverage Driven Functional Verification on RISC-V Cores

Design Verification is critical to proving functional correctness and establishing confidence in a design. Several studies from industry and academia, particularly over the course of the last two decades, have explored various verification methodologies that fall somewhere between dynamic or purely static formal approaches.

Random stimulus methods perform better because they eventually cover many cases. Most new ideas in dynamic verification over the last two decades have largely been towards semi formal verification methodologies such as coverage driven verification and constrained test generation. In this paper, we explore an approach to dynamic functional verification that we use at the RISE lab, IIT Madras for the verification of the RISC-V based Shakti cores.

Padframe Generator for RTL2GDS flow

This paper describes an opensource padframe generator that was developed on the efabless platform for usage with the Open-Source Qflow Digital Synthesis Flow, for digital logic chips in the X-FAB XH018, 180nm process. It is presented by Philipp, who is a software developer with a strong background in security and cryptography. He is currently learning microelectronics.

Rapid Physical IC Implementation

“Rapid Physical IC Implementation and Integration using Efabless Platform”. This paper describe a rapid backend process flow (synthesis, placement, STA, routing) and top level integration to implement a small RTL IP into a tapeout ready chip using the Efabless online platform

SiFive RISCV Symposium Day 2 – Bangalore, the land of AI/ML

AI and machine learning (branch of AI) needs deep neural networks, which in turn requires high-performance computing. SiFive and RISC-V organization were happy to announce a solution, tailored to this requirement to AI/ML start-ups in Bangalore on 23rd August

SiFive RISCV Symposium Day 1 – Blockbuster opening at Hyderabad

The tech symposium started with Krste’s talk on “History of RISC-V Ecosystem around the world”. The talk started from very basic topic like “Why Instruction Set Architecture Matters?” and ended on a very important note on the need of a FREE ISA. He also provided ideas on how chip design factories can become company like Instagram, which exactly is everybody’s vision of abstracting details, and take advantage of existing online infrastructure

RISC-V enters India and VSD personally invite you…

We would like to invite you to attend one of the SiFive & Open-Silicon Tech Symposiums taking place at six different locations throughout India in August. See map in below image for exact locations and date of events.

I would be presenting a very important tutorial, which closely connects open-source ISA implementation to open-source EDA tools – “How to design complex RISC-V SoC with open-source EDA tools and time to productize design ideas?”

From concept to algorithm – RISC-V floating point addition

First thing which comes in the title is “concept”, which is the simple one. It says, if I want to add 2 floating-point numbers, I simply add them. Second, “algorithm” is the details for a computer, how it will add 2 floating-point numbers.Third, which is “RISC-V”, which deals with binary numbers, describes how can you use same concept and algorithm to do a “binary floating-point addition”

Opensource hierarchical physical design update on RISC-V SoC

Few months back, I had posted the below floorplan of picoSoC, which is a simple (yet powerful) example of SoC using picoRV32, which can run code directly from SPI flash chip and can be used as a turn-key solution for trivial tasks in ASIC and FPGA designs

RISC-V Workshop @IIT Madras – Day 2

RISC-V workshop was concluded by Rick O’ Connor and Prof. Kamakoti. Rick pointed out one important opportunity, with which we started a blog i.e. “How can you and I start a processor company?”

RISC-V Workshop @IIT Madras – Day 1

A keynote from Rick O’ Connor, executive director, RISC-V foundation, and we remember this to core of our heart, because of the below statement he made – “RISC-v is present in 27 countries and can be used by 57 % of population of World soon” That’s the spread of open-source ISA

Coverage Driven Functional Verification on RISC-V Cores

Padframe Generator for RTL2GDS flow

Rapid Physical IC Implementation

SiFive RISCV Symposium Day 2 – Bangalore, the land of AI/ML

SiFive RISCV Symposium Day 1 – Blockbuster opening at Hyderabad

RISC-V enters India and VSD personally invite you…

From concept to algorithm – RISC-V floating point addition

Opensource hierarchical physical design update on RISC-V SoC

RISC-V Workshop @IIT Madras – Day 2

RISC-V Workshop @IIT Madras – Day 1

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