Blogs – Page 3 – VLSI System Design

VSD-HDP : Verilator Verification Environment for RISC-V vector accelerator

In a nutshell, the project really is to build a Verilator Verification environment i.e. a structure in which we can set up testbenches that are executed with Verilator. The thing which is interesting in this project is we are going to tie that Verilator piece with a golden model arithmetic library and that is going to be something that you can publish as nobody else in the world has that

It’s a Verilator Testbench environment that uses an online arithmetic library to generate the right bit pattern. We are not using randoms, but we are using a Golden model. If you progress from ALU to a vector accelerator, you will have a vector lane, vector register file, vector load/store unit, vector instructions.

Skywater130 Spec to GDS workshop details

You might have seen the above image in one form or another, in different our blogs or VSD websites. Every trapezoid in above image is […]

What I did in 8-weeks-VSD Internship? – Vezzal

Constant development of tools often breaks something internally which can lead to other issues. Hence there is a need to test the tool for its previous supporting features. But the tool needs an environment to get launched and good test cases to test the features. This is called as “Continuous Integration (CI)”. I

VSDBabySoC delivered under VSD-HDP Intern

Mohammad joined VSD as a part of 8-week Hardware Design Program (HDP), which is specially designed for anyone looking to reach utmost level of VLSI from scratch.

Chip Tape-out – Not a dream anymore – VSD students prove it again

From nothing to Tapeout Ready basic designs – These 7 students have seen it all. Congratulations to all of them. Great start to their semiconductor career.
Here’s the link with their design details-

VSD delivered 1st online analog tapeout workshop using Sky130

VSD promises to deliver similar IP design workshops in upcoming days, followed by the next big leap – SoC design workshop with VSD SoC generator using all VSD IPs developed by VSD community using Skywater 130 nm technology node.

“What I did in the 5-day Advanced Physical Design workshop?” – Experiencing the “freedom within expanding boundaries”

I have been tracking opensource tools in backend flow and also VSD’s online programs like MYTH, Digital System Design, Modelling using Verilog etc. In the […]

What I did in 8-weeks-VSD Internship? On-chip PLL using Sky130

In this 8-week internship I spent the first week on researching existing work and making design decisions for the PLL components namely – Phase Frequency Detector, Charge Pump, Voltage Controlled Oscillator and Frequency Divider. I also looked into linking of the Sky130nm PDK with SPICE for the circuit implementation.

What can I do in 5-day VSD Workshop? Learn TL-Verilog and RISC-V

RISC-V and open-source hardware is undoubtedly destined to change the industry. Not just for the ISA and design, there are ongoing efforts to tape out an actual chip with completely open-source tools!
Join the revolution!

What I did in 5-day VSD – Workshop? Designed basic RISC-V core

A few months back, I came across a workshop titled ‘RISC-V based Microprocessor for You in Thirty Hours (MYTH)’, that was about designing RISC-V core […]