Chip Tape-out – Not a dream anymore – VSD students prove it again

Let's again take a backseat and congratulate 7 students out of 3000 eSim Marathon participants nationwide, which was conducted jointly by VSD and FOSSEE, IIT Bombay. These 7 students dared to take their eSim Marathon designs till GDSII level, which is now silicon ready with Skywater 130nm technology. 7 out of 3000 is close to 0.23% which means these 7 students are among the top 0.23% of our country's best minds. Can you believe that?

Another few amazing facts about these 7 participants - 8-weeks back, they had absolutely zero clue about what circuit design is except the full-form. Thanks to Prof. Kannan Moudgalya and his team from FOSSEE, IIT Bombay, who dreamt of producing a large number of circuit designers from our country and developed "eSim opensource circuit design tool" which is a simple GUI based platform built specially for freshers. Prof. Kannan Moudgalya didn't stop there but organized the world's largest "Circuit design marathon" where 3000+ participants from whole India were selected for the first round.

We put a process in place which filtered the best circuit designers and 138 participants qualified for the marathon in 3 weeks. VSD took a step ahead and invited all winners for a 4-week open challenge of circuit layout using Skywater 130 nm technology node (since we used the same technology for eSim Marathon). They were provided basic guidance and then left in the ocean to learn. Just like an ocean, waves try to knock you down - Sky130, metal layers, RTL2GDS, MAGIC - All these waves tried to knock them down too. Finally 7 participants fought them back and now they own the ocean

From nothing to Tapeout Ready basic designs - These 7 students have seen it all. Congratulations to all of them. Great start to their semiconductor career.
Here's the link with their design details-

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Posted in Google/SKywater130, IP design, Open Source, RISC-V, Tapeout, Tool related, VSD-IAT.

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