VSD-HDP : Verilator Verification Environment for RISC-V vector accelerator

In a nutshell, the project really is to build a Verilator Verification environment i.e. a structure in which we can set up testbenches that are executed with Verilator. The thing which is interesting in this project is we are going to tie that Verilator piece with a golden model arithmetic library and that is going to be something that you can publish as nobody else in the world has that

It’s a Verilator Testbench environment that uses an online arithmetic library to generate the right bit pattern. We are not using randoms, but we are using a Golden model. If you progress from ALU to a vector accelerator, you will have a vector lane, vector register file, vector load/store unit, vector instructions.

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What I did in 8-weeks-VSD Internship? On-chip PLL using Sky130

In this 8-week internship I spent the first week on researching existing work and making design decisions for the PLL components namely – Phase Frequency Detector, Charge Pump, Voltage Controlled Oscillator and Frequency Divider. I also looked into linking of the Sky130nm PDK with SPICE for the circuit implementation.

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What I did in 8-weeks-VSD Internship? – Open Source Power Analysis Tool Using Python

Power analysis has materialized as a principal theme in today’s world in semiconductor industries. As very large scale integrated circuit (VLSI) are far beyond from human ability because of complexity in nature. So to analyse power in these circuits we use open source computer aided tools, plenty of tools are available but most of them are costly. I designed an open source power analysis tool for the academic use. This tool gives out values of average and leakage power of any circuit by just giving the netlist of circuit file along with name of supply voltage as input. This tool is designed in python language.

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