Concepts | VLSI System Design

IITM Student Registration

Welcome to first ever online semiconductor technology conference with prime focus to build SoC using RISC-V CPU using Open-source EDA tool on 27th October 2018, 8:00 AM to 3:00 PM
(https://www.vlsisystemdesign.com/vsdopen2018-2/)

Free registration for IITM Participants:
Online viewing Zoom link will be send 12 hours in advance.
Alternatively, IITM view point: A.M. Turing Hall (BSB 361)

Please register using the form below, its on first come first serve basis.
Contact us at 8548037643 or vsd@vlsisystemdesign.com

SiFive RISCV Symposium Day 2 – Bangalore, the land of AI/ML

AI and machine learning (branch of AI) needs deep neural networks, which in turn requires high-performance computing. SiFive and RISC-V organization were happy to announce a solution, tailored to this requirement to AI/ML start-ups in Bangalore on 23rd August

SiFive RISCV Symposium Day 1 – Blockbuster opening at Hyderabad

The tech symposium started with Krste’s talk on “History of RISC-V Ecosystem around the world”. The talk started from very basic topic like “Why Instruction Set Architecture Matters?” and ended on a very important note on the need of a FREE ISA. He also provided ideas on how chip design factories can become company like Instagram, which exactly is everybody’s vision of abstracting details, and take advantage of existing online infrastructure

RISC-V enters India and VSD personally invite you…

We would like to invite you to attend one of the SiFive & Open-Silicon Tech Symposiums taking place at six different locations throughout India in August. See map in below image for exact locations and date of events.

I would be presenting a very important tutorial, which closely connects open-source ISA implementation to open-source EDA tools – “How to design complex RISC-V SoC with open-source EDA tools and time to productize design ideas?”

From concept to algorithm – RISC-V floating point addition

First thing which comes in the title is “concept”, which is the simple one. It says, if I want to add 2 floating-point numbers, I simply add them. Second, “algorithm” is the details for a computer, how it will add 2 floating-point numbers.Third, which is “RISC-V”, which deals with binary numbers, describes how can you use same concept and algorithm to do a “binary floating-point addition”

Opensource hierarchical physical design update on RISC-V SoC

Few months back, I had posted the below floorplan of picoSoC, which is a simple (yet powerful) example of SoC using picoRV32, which can run code directly from SPI flash chip and can be used as a turn-key solution for trivial tasks in ASIC and FPGA designs

RISC-V Workshop @IIT Madras – Day 2

RISC-V workshop was concluded by Rick O’ Connor and Prof. Kamakoti. Rick pointed out one important opportunity, with which we started a blog i.e. “How can you and I start a processor company?”

RISC-V Workshop @IIT Madras – Day 1

A keynote from Rick O’ Connor, executive director, RISC-V foundation, and we remember this to core of our heart, because of the below statement he made – “RISC-v is present in 27 countries and can be used by 57 % of population of World soon” That’s the spread of open-source ISA

A tribute to opensource (EDA and ISA)

Since then, we have promoted courses using a lot of open-source EDA tools like Opentimer for STA, qflow for Physical design, TL-verilog for pipelining, Yosys for Synthesis, Proton for EDA and many more. Not only that, we have organized an online conference (as you might be aware) and here’s the link with details:

https://www.vlsisystemdesign.com/vsdopen2018-2/

Inception of “bias” in IEEE754 floating point standard

how the IEEE754 floating point standard designed the way it is. Every great design begins with an even better story. We all must have read blogs and watched videos about how to convert a decimal floating-point number to its binary form. We must have seen standard formulas of converting an IEEE754 standard floating-point number to its decimal form.