Now that’s the beauty of open-source….
Hey There, Our team worked really hard to get Robot + MP3 player using India’s First Indegenious 32-bit RISC-V Microprocessor “Shakti E-Class”…This one is Shakti […]
Category Archives: Concepts
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Think about pre-placed cells and power ring generation in opensource EDA
Hey There – Think about it!! Today’s version of open-source EDA tools, work very well for hierarchical designs sub-25k instance count. For hierarchical designs ~500k […]
Re-define pad placement using open-source EDA
Hey There – Think about it!!! Last week, we shared our idea and vision of “How to define the width and height of core and […]
Let’s re-think open-source EDA – core and die
Hey There – Think about it!!! Today’s version of open-source EDA tools, work very well for hierarchical designs sub-25k instance count. For hierarchical designs ~500k […]
‘Made in India’ SHAKTI processor on VSDFLOW – Now that’s exciting
With learning being online, SHAKTI core and ‘vsdflow’ being opensource, this is first-time in the history of VLSI design & EDA (thanks to RISC-V ecosystem and Shakti Team at IITM lead by Prof. Kamakoti), a chip will ever be taped-out using all open source flow, which will cater to almost 80% Indian Semiconductor Market.
Keynote 1(Continued): Inception of Intel 8086
It wasn’t that bigger deal for Intel because they thought, at the time, it will be 250,000 chips will be sold for 5 years, which isn’t that many. But they were wrong. It was a 100Million computers were sold. And suddenly 8086 from being an emergency back-up was an over-night success and had a very bright future, because it was binary compatible of PC software, and so had great opportunity
Isn’t that an inspiring story?
A new golden age for computer architecture by Prof. David Patterson
In last 50 years, there are 3 lessons that we can draw. First – software advances can inspire architecture innovations. Second – when we raise the hardware/software interface, it creates opportunities for architecture innovation. Third – in our field, the way we settle these debates, isn’t by just arguing in a bar, rather people spent/invest billions of dollars to investigate their ideas and marketplace settles these debates
History etched with VSDOpen2018 – First VLSI online conference….
Hi “Pictures speak it all” Finally, we all did it – VSDOpen – first ever online VLSI conference. Very close to a real one – […]
Conclusion: Time to productize and monetize your open-source Idea with VSD
“Design at $0” is an initiative driven by our team at VSD.Working in open environment is much easier process as all the resources are openly available, but here arise the loophole.
Paper 7: Top-Down Transaction-Level Design with TL-Verilog
Transaction-Level Verilog (TL-Verilog) is an emerging extension to SystemVerilog that supports transaction-level design methodology. In transaction-level design, a transaction is an entity that moves through a microarchitecture. It is operated upon and steered through the machinery by flow components such as pipelines, arbiters, and queues. A transaction might be a machine instruction, a flit of a packet, or a memory read/write. The flow of a transaction can be established independently from the logic that operates on the transaction. We present a preliminary library of TL-Verilog flow components that can be quickly stitched together to establish a complete microarchitecture. We show how transaction logic, like packet decoding, can be added within this flow.
