Mohamed Kassem is the CTO and Co-Founder of efabless.com, the first semiconductor company applying open community innovation to all aspects of product development. Prior to launching efablesshe […]
An opensource padframe generator was developed on the efabless platform for usage with the Open-Source Qflow Digital Synthesis Flow, for digital logic chips in the X-FAB XH018, 180nm process.
VSDOpen 2018 Keynote 1 : A New Golden Age for Computer Architecture: History, Challenges, and Opportunities
A New Golden Age for Computer Architecture: History, Challenges, and Opportunities, David Patterson, UC Berkeley and Google, October 26, 2018Full Turing Lecture: https://www.acm.org/hennessy-patterson-turing-lecture
Welcome to first ever online semiconductor technology conference with prime focus to build SoC using RISC-V CPU using Open-source EDA tool on 27th October 2018, 8:00 AM to 3:00 PM
Free registration for IITM Participants:
Online viewing Zoom link will be send 12 hours in advance.
Alternatively, IITM view point: A.M. Turing Hall (BSB 361)
Please register using the form below, its on first come first serve basis.
Contact us at 8548037643 or email@example.com
AI and machine learning (branch of AI) needs deep neural networks, which in turn requires high-performance computing. SiFive and RISC-V organization were happy to announce a solution, tailored to this requirement to AI/ML start-ups in Bangalore on 23rd August
The tech symposium started with Krste’s talk on “History of RISC-V Ecosystem around the world”. The talk started from very basic topic like “Why Instruction Set Architecture Matters?” and ended on a very important note on the need of a FREE ISA. He also provided ideas on how chip design factories can become company like Instagram, which exactly is everybody’s vision of abstracting details, and take advantage of existing online infrastructure
We would like to invite you to attend one of the SiFive & Open-Silicon Tech Symposiums taking place at six different locations throughout India in August. See map in below image for exact locations and date of events.
I would be presenting a very important tutorial, which closely connects open-source ISA implementation to open-source EDA tools – “How to design complex RISC-V SoC with open-source EDA tools and time to productize design ideas?”
First thing which comes in the title is “concept”, which is the simple one. It says, if I want to add 2 floating-point numbers, I simply add them. Second, “algorithm” is the details for a computer, how it will add 2 floating-point numbers.Third, which is “RISC-V”, which deals with binary numbers, describes how can you use same concept and algorithm to do a “binary floating-point addition”
Few months back, I had posted the below floorplan of picoSoC, which is a simple (yet powerful) example of SoC using picoRV32, which can run code directly from SPI flash chip and can be used as a turn-key solution for trivial tasks in ASIC and FPGA designs
RISC-V workshop was concluded by Rick O’ Connor and Prof. Kamakoti. Rick pointed out one important opportunity, with which we started a blog i.e. “How can you and I start a processor company?”