With learning being online, SHAKTI core and ‘vsdflow’ being opensource, this is first-time in the history of VLSI design & EDA (thanks to RISC-V ecosystem and Shakti Team at IITM lead by Prof. Kamakoti), a chip will ever be taped-out using all open source flow, which will cater to almost 80% Indian Semiconductor Market.
It wasn’t that bigger deal for Intel because they thought, at the time, it will be 250,000 chips will be sold for 5 years, which isn’t that many. But they were wrong. It was a 100Million computers were sold. And suddenly 8086 from being an emergency back-up was an over-night success and had a very bright future, because it was binary compatible of PC software, and so had great opportunity
Isn’t that an inspiring story?
In last 50 years, there are 3 lessons that we can draw. First – software advances can inspire architecture innovations. Second – when we raise the hardware/software interface, it creates opportunities for architecture innovation. Third – in our field, the way we settle these debates, isn’t by just arguing in a bar, rather people spent/invest billions of dollars to investigate their ideas and marketplace settles these debates
Hi “Pictures speak it all” Finally, we all did it – VSDOpen – first ever online VLSI conference. Very close to a real one – […]
“Design at $0” is an initiative driven by our team at VSD.Working in open environment is much easier process as all the resources are openly available, but here arise the loophole.
Transaction-Level Verilog (TL-Verilog) is an emerging extension to SystemVerilog that supports transaction-level design methodology. In transaction-level design, a transaction is an entity that moves through a microarchitecture. It is operated upon and steered through the machinery by flow components such as pipelines, arbiters, and queues. A transaction might be a machine instruction, a flit of a packet, or a memory read/write. The flow of a transaction can be established independently from the logic that operates on the transaction. We present a preliminary library of TL-Verilog flow components that can be quickly stitched together to establish a complete microarchitecture. We show how transaction logic, like packet decoding, can be added within this flow.
This paper introduces TL-V erilog and W ARP-V and then describes the formal verification of WARP-V using riscv-formal, a formal verification framework for RISC-V. Timing-abstraction and transaction-level design are showing significant benefits for hardware modeling, but this is the first demonstration of their benefits for verification modeling. As evidence of these benefits, the verification of all RISC-V configurations of WARP-V is accomplished in a single page of code.
Steve Hoover is the founder of Redwood EDA. Steve holds a BS in electrical engineering from Rensselaer Polytechnic Institute and an MS in computer science from the University of Illinois. He has designed numerous components for high-performance server CPUs and network architectures for DEC, Compaq, and Intel. Students will learn Transaction-Level Verilog modelingtechniques to generate Verilog models in half the time using the makerchip.comfree online IDE. A new open-source RISC-V CPU development effort will be introduced that showcases flexible IP design practices.
This paper describe a rapid backend process flow (synthesis, placement, STA, routing) and top level integration to implement a small RTL IP into a tapeout ready chip using the Efabless online platform . The full process is completed in less than 3 hours. The IP implemented is a configurable frequency divider
Design Verification is critical to proving functional correct- ness and establishing confidence in a design. Several stud- ies from industry and academia, particularly over the course of the last two decades, have explored various verifica- tion methodologies that fall somewhere between dynamic or purely static formal approaches.
System-on-Chips (SoCs) today have become extremely complex structures housing heavily optimized cores, count- less peripherals, and large interconnect fabrics. Even re- stricting ourselves to just verifying the microprocessor, the state space to be verified is enormous and cannot be exhaus- tively explored in any finite amount of time. Manually writ- ten tests, while effective at capturing some complexities of design intent, suffer from the fact that they are expensive in cost and time required to develop them. Random stimulus methods perform better because they eventually cover many cases. Most new ideas in dynamic verification over the last two decades have largely been towards semi formal verifi- cation methodologies such as coverage driven verification and constrained test generation. In this paper, we explore an approach to dynamic functional verification that we use at the RISE lab, IIT Madras for the verification of the RISC-V based Shakti cores.