History etched with VSDOpen2018 – First VLSI online conference….

Hi

“Pictures speak it all”

Finally, we all did it – VSDOpen – first ever online VLSI conference. Very close to a real one – The energy, the keynotes, the presentations – they all were so perfect. VSD would like to thank all participants, keynote speakers and presenters from all over the world, who came together and made this dream a reality.

As shown in above pic, people from all over world met on single virtual stage, shared ideas, networked with each other, exchanged email id’s, discussed business – all online. This was a dream come true and next year, it will be bigger and better, with a mix-n-match of virtual plus physical conference, where speakers as well as attendees will have the option to physically come over to venue to attend or attend online. VSD will make sure, they take back home the same experience, just like a physical conference

Conference started with keynote speech from Prof. David Patterson on “A new golden age for computer architecture: History, challenges and opportunities”

Mainly, this talk focused on lessons of last 50 years of computer architecture, where Prof. David briefed everyone about software advances that can inspire architecture innovations, raising hardware/software interface which creates opportunities for architecture innovation and debates about how ultimately marketplace settles for an architecture

Next keynote was from Sharon Hu, about “Professional growth with ACM SIGDA

This talk was mostly for young engineers in field of VLSI & Semiconductors, where Sharon discussed about techniques for professional growth in multiple dimension, like, knowledge bowl, networking, innovate and recognition. She also mentioned about SIGDA sponsored events and how can you be a part of it

This talk was followed by a contest announcement by George J. Chen, Timing Domain Lead, Programmable Solutions group, Intel and the contest is named “TAU Contest 2019

Some background about TAU contest – Its an ACM international workshop on Timing issues in the specifications & synthesis of digital systems and scope of topics are all aspects related to static timing analysis like delay calculation, statistical static timing analysis, incremental timing analysis, crosstalk effects, interaction with IT drop, power and yield analysis, model extraction, latch/asynchronous circuit modelling, and many more

Next, we entered our first paper presentation on physical design by Philipp Gühring, who is a software developer with a strong background in security and cryptography. His topic was “Padframe generator for qflow

Philipp future ideas is to enhance Padframe generator to generate pad frames for multiple cores inside the chip.

Following this, was a very interesting talk by Mohamed Kassem, Co-founder & CTO of efabless.com, where he discussed about “Applying open community innovation to hardware product creation

Mohamed had a very simple solution to markets biggest needs in IOT world – it needs as many products as possible, as quickly as possible, shortest time to market and rapid market feedback. Solution – A community-based approach provides the scale, access and economics required for IoT

efabless open platform is very intuitive and has powerful design request process connecting customers with engineering entities. It has a marketplace for community-developed design solutions. Just like an app-store, but for IP and IC reference designs. Most importantly, it has design flow based on open-source tools with no upfront cost and obfuscated PDK. Very innovative, very powerful and seamless GUI for users. You might want to check about it on efabless.com

Next was a paper presentation on physical design by Anand Rajgopalan from Mumbai University, whose topic was “Placement and routing of digital core IC to pads using cloud-based EDA tools

He had very interesting findings about process design flow of frequency divider chip using cloud open-source EDA tools. He used frontend CloudV tools from efabless.com. He also demonstrated placement & routing of synthesized core chip to IO pads followed by addition of substrate and antenna tie-down

Next paper was based on SHAKTI RISCV processor – India’s first micro-processor, and was presented by Lavanya J., Anmol Sahoo and Paul George from SHAKTI group, CSE dept., RISE lab, IIT Madras

The paper was focused on “Coverage driven functional verification on RISC-V cores

Highlights of problems, which SHAKTI team observed are that design verification is a multifaceted issue. There are multiple approaches like directed testing, formal verification, random testing, but each method has its own tradeoff

SHAKTI team’s view on this was that random testing is a promising approach. It can detect bugs early in design process. It can generate corner cases with less effort as compared to directed testing. Again, there are problems involved like controllability is hard, coverage can be an issue and maintaining multiple test environments is difficult

SHAKTI team believed ‘feedback’ will address previous issues. Giving constant feedback to random generator can enhance the test suite and decided to use ‘coverage’ as a metric. Using this along with a lock-step verification framework can automate this process

Another paper was on Physical design by Alberto Gomez Saiz from Imperial college London. The topic was “Rapid Physical IC implementation and integration using efabless platform

You can think of this paper as a summary of open-source flow for full backend and integration for small RTL design on efabless platform, with zero cost, which took less than 3hours. The same design (frequency divider) was used along with 0.18um XFAB “6 metal”

Being in the forum of open-source physical design flow, we thought of bringing our presentation right at this point, which was a tutorial on “How to design complex RISC-V SoC using open-source EDA Tools?” and “Time to productize/monetize your idea” This was presented by me and Anagha Ghosh, both serve as Director of VLSI System Design Corp. Pvt. Ltd.

This was focused on 5 different problems associated with chip design for a startup or an individual contributor – viz. 1) RTL procurement – solved by many open-source high-quality RISC-V RTL available on github 2) RTL design concepts & architecture understanding – solved by high-quality online tutorials available on https://www.vlsisystemdesign.com/   3) Industry grade EDA tools – solved by open-source eda tools 4) Guidance on how to use open-source tools – solved by high class tutorial on https://www.vlsisystemdesign.com/ on how to use open-source tools 5) Why would you want to build RISC-V SoC? – Solved by cloud-based revenue sharing technique by VSD.

This marked an end for all back-end related papers.

Next, we started with front-end presentation and Steve Hoover from Redwood EDA gave an extremely concise “Front-end symposium intro

Steve brought into notice 4 barriers to open-source hardware 1) Access to tools – solved by complete open-source FPGA design flows 2) Access tp hardware – solved using cloud FPGA’s 3) Complexity and scalability – TL-Verilog is the answer 4) Patents – we will get back on this

Steve’s http://makerchip.com/  has in-browser access to tools and solves almost all barriers mentioned above

This presentation was followed by 2 more presentations on TL-Verilog

One by Akos Hadnagy, TU Delft, whose presentation was on “Formal verification on WARP-V

The goal of WARP-V was flexibility i.e. to leverage and showcase TL-verilog to build the world’s most flexible CPU core IP. Flexibility is tough, as small conceptual variation requires extensive RTL parametrization of staging (flip-flops), stitching through hierarchy, clock gating/enabling and many more. SystemC with HLS is not ideal for CPU’s with tight cycle-level interactions.

The 2 best approaches 1) Macro Preprocessor (M4) provides parametrization, component selection and code generation. 2) Transaction-Level verilog (TL – X.org) implies from context and does staging, stitching through hierarchy and clock gating/enabling.

WARP-V was brought to life using 11-instruction test program and remaining verification was done using formal tools (riscv-formal by Clifford wolf), from early stages of development

Final presentation was from Ahmed Salman, from Alexandria University and his topic was “Top-Down transaction-level design with TL-Verilog

He talked about top-down design (start design from overall description and end design with smallest detail), timing-abstract circuit design, transaction-level design, lexical re-entrance and generic library (combination flow components, like arbiters)

All papers can be found in below link:

https://www.vlsisystemdesign.com/vsdopen-2018-keynote-paper/

This way, on 27th October, 2018 – the first online VLSI conference was held and all of us.

And, if we become as successful as DAC, in upcoming years, then all presenters and participants at VSDOpen2018 become a part of history

Registration for Ethical RISC-V IoT Workshop

Welcome to Ethical RISC-V IoT Workshop

The “Ethical RISC-V IoT Workshop” at IIIT Bangalore, organized in collaboration with VSD, is a structured, educational competition aimed at exploring real-world challenges in IoT and embedded systems. Participants progress through three stages: building an application, injecting and managing faults, and enhancing application security. The event spans from May 9 to June 15, 2024, culminating in a showcase of top innovations and an award ceremony. This hands-on hackathon emphasizes learning, testing, and securing applications in a collaborative and competitive environment.

Rules :
  1. Only for Indian Student whose college is registered under VTU
  2. Only team of 2 members can Register
  3. Use only VSDSquadron Mini resources for product development
Awards :
  1. Prize money for final 10 Team
  2. 3 Winner team’s Product will be evaluated for Incubation
  3. 7 consolation prizes
  4. Completion Certificate to final round qualifier
  5. Chance to build a Proud Secured RISC-V Platform for India

Date for Registration : 9th May - 22nd May, 2024
Hackathon Inauguration : 23rd May 2024

VSDSquadron (Educational Board)

VSDSquadron, a cutting-edge development board based on the RISC-V architecture that is fully open-source. This board presents an exceptional opportunity for individuals to learn about RISC-V and VLSI chip design utilizing only open-source tools, starting from the RTL and extending all the way to the GDSII. The possibilities for learning and advancement with this technology are limitless.

Furthermore, the RISC-V chips on these boards should be open for VLSI chip design learning, allowing you to explore PNR, standard cells, and layout design. And guess what? vsdsquadron is the perfect solution for all your needs! With its comprehensive documentation and scalable labs, thousands of students can learn and grow together.

VSD HDP (Hardware Design Program) Duration-10 Week

With VSD Hardware Design Program (VSD-HDP),  you have the opportunity to push the boundaries of what exist in open source and establish the new benchmark for tomorrow.

It will leverage your degree in Electrical or Computer Engineering to work with

  • Programmable logic
  • Analog/ digital IP
  • RISC-V
  • Architecture & microprocessors
  • ASICs and SoCs on high-density digital or RF circuit cards
  • Gain hands-on knowledge during design validation and system integration.

Sounds exciting to just get started with expert mentors, doesn’t it? But we are looking for the next generation of learners, inventors, rebels, risk takers, and pioneers.

“Spend your summer working in the future !!”

Outcomes of VSD Online Research IP Design Internship Program

  1. Job opportunities in Semiconductor Industry
  2. Research work can be submitted to VLSI International journals
  3. Participate in Semiconductor International Conference with Internship Research Work
  4. Paper Publications in IEEE Conference and SIG groups
  5. Tape out opportunity and IP Royalty
  6. Interact with world class Semiconductor designer and researchers
  7. Academic professions where more research projects are encouraged.
  8. All the above research and publication work will help colleges and institutes to improve accreditation levels.

Know More Information

VSD – Intelligent Assessment Technology (VSD-IAT)

VSD – Intelligent Assessment Technology (VSD-IAT) is expertly built training platform and is suited for designer requirements. Semiconductor companies understand the value of training automation and Engineer performance enhancement, and do not need to be convinced of the impact of a virtual platform for learning. VSD trainings are quick, relevant, and easy to access from any device at any time zone.

VSD Intern Webinars

VSD Interns made it happen !!

VSD is working towards creating innovative talent pool who are ready to develop design and products for the new tech world. VSD believes in “Learning by doing principle” , and always prepare the student to apply the knowledge learned in the workshops, webinars and courses. We always push our students to work on new designs, test it and work continuously till it becomes the best performing design. Any student who enrolls to VSD community starts working with small design and grows with us and develops a tapeout level design with complete honesty and dedication towards the Work !!

Check out VSD Interns Achievement!

VSDOpen Online Conference

Welcome to the World’s only online conference in Semiconductor Industry VSDOpen Conference. With enormous support and global presence of audience from different segments of industrial lobby and academia made a highly successful event. Evolution is change in the genetic makeup of a population over time, online conference is one kind evaluation everyone adapt soon. 

  • VSDOpen 2022 is an online conference to share open-source research with the community and promote  hardware design mostly done by the student community.
  • VSDOpen 2022 is based on the theme “How to lower the cost to learn, build, and tapeout chips ?”  , which will provide a platform to community to build stronger designs and strengthen the future of Chip design.
  • VSDOpen is envisioned to create a community based revolution in semiconductor hardware technology.
  • The open source attitude is required to bring out the talent and innovation from the community who are in remote part of world and have least access to the technologies.  And now Google support will help to bring the vision to execution by VSD team

VSD Online Course by Kunal Ghosh

VSD offers online course in complete spectrum of vlsi backend flow from RTL design, synthesis and Verification, SoC planning and design, Sign-off analysis, IP Design, CAD/EDA automation and basic UNIX/IT, Introduction to latest technology – RISC-V, Machine intelligence in EDA/CAD, VLSI Interview FAQ’s.

Current Reach – As of 2021, VSD and its partners have released 41 online VLSI courses and was successfully able to teach  ~35900 Unique students around 151 countries in 47 different languages, through its unique info-graphical and technology mediated learning methods.

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