“Pictures speak it all”
Finally, we all did it – VSDOpen – first ever online VLSI conference. Very close to a real one – The energy, the keynotes, the presentations – they all were so perfect. VSD would like to thank all participants, keynote speakers and presenters from all over the world, who came together and made this dream a reality.
As shown in above pic, people from all over world met on single virtual stage, shared ideas, networked with each other, exchanged email id’s, discussed business – all online. This was a dream come true and next year, it will be bigger and better, with a mix-n-match of virtual plus physical conference, where speakers as well as attendees will have the option to physically come over to venue to attend or attend online. VSD will make sure, they take back home the same experience, just like a physical conference
Conference started with keynote speech from Prof. David Patterson on “A new golden age for computer architecture: History, challenges and opportunities”
Mainly, this talk focused on lessons of last 50 years of computer architecture, where Prof. David briefed everyone about software advances that can inspire architecture innovations, raising hardware/software interface which creates opportunities for architecture innovation and debates about how ultimately marketplace settles for an architecture
Next keynote was from Sharon Hu, about “Professional growth with ACM SIGDA”
This talk was mostly for young engineers in field of VLSI & Semiconductors, where Sharon discussed about techniques for professional growth in multiple dimension, like, knowledge bowl, networking, innovate and recognition. She also mentioned about SIGDA sponsored events and how can you be a part of it
This talk was followed by a contest announcement by George J. Chen, Timing Domain Lead, Programmable Solutions group, Intel and the contest is named “TAU Contest 2019”
Some background about TAU contest – Its an ACM international workshop on Timing issues in the specifications & synthesis of digital systems and scope of topics are all aspects related to static timing analysis like delay calculation, statistical static timing analysis, incremental timing analysis, crosstalk effects, interaction with IT drop, power and yield analysis, model extraction, latch/asynchronous circuit modelling, and many more
Next, we entered our first paper presentation on physical design by Philipp Gühring, who is a software developer with a strong background in security and cryptography. His topic was “Padframe generator for qflow”
Philipp future ideas is to enhance Padframe generator to generate pad frames for multiple cores inside the chip.
Following this, was a very interesting talk by Mohamed Kassem, Co-founder & CTO of efabless.com, where he discussed about “Applying open community innovation to hardware product creation”
Mohamed had a very simple solution to markets biggest needs in IOT world – it needs as many products as possible, as quickly as possible, shortest time to market and rapid market feedback. Solution – A community-based approach provides the scale, access and economics required for IoT
efabless open platform is very intuitive and has powerful design request process connecting customers with engineering entities. It has a marketplace for community-developed design solutions. Just like an app-store, but for IP and IC reference designs. Most importantly, it has design flow based on open-source tools with no upfront cost and obfuscated PDK. Very innovative, very powerful and seamless GUI for users. You might want to check about it on efabless.com
Next was a paper presentation on physical design by Anand Rajgopalan from Mumbai University, whose topic was “Placement and routing of digital core IC to pads using cloud-based EDA tools”
He had very interesting findings about process design flow of frequency divider chip using cloud open-source EDA tools. He used frontend CloudV tools from efabless.com. He also demonstrated placement & routing of synthesized core chip to IO pads followed by addition of substrate and antenna tie-down
Next paper was based on SHAKTI RISCV processor – India’s first micro-processor, and was presented by Lavanya J., Anmol Sahoo and Paul George from SHAKTI group, CSE dept., RISE lab, IIT Madras
The paper was focused on “Coverage driven functional verification on RISC-V cores”
Highlights of problems, which SHAKTI team observed are that design verification is a multifaceted issue. There are multiple approaches like directed testing, formal verification, random testing, but each method has its own tradeoff
SHAKTI team’s view on this was that random testing is a promising approach. It can detect bugs early in design process. It can generate corner cases with less effort as compared to directed testing. Again, there are problems involved like controllability is hard, coverage can be an issue and maintaining multiple test environments is difficult
SHAKTI team believed ‘feedback’ will address previous issues. Giving constant feedback to random generator can enhance the test suite and decided to use ‘coverage’ as a metric. Using this along with a lock-step verification framework can automate this process
Another paper was on Physical design by Alberto Gomez Saiz from Imperial college London. The topic was “Rapid Physical IC implementation and integration using efabless platform”
You can think of this paper as a summary of open-source flow for full backend and integration for small RTL design on efabless platform, with zero cost, which took less than 3hours. The same design (frequency divider) was used along with 0.18um XFAB “6 metal”
Being in the forum of open-source physical design flow, we thought of bringing our presentation right at this point, which was a tutorial on “How to design complex RISC-V SoC using open-source EDA Tools?” and “Time to productize/monetize your idea” This was presented by me and Anagha Ghosh, both serve as Director of VLSI System Design Corp. Pvt. Ltd.
This was focused on 5 different problems associated with chip design for a startup or an individual contributor – viz. 1) RTL procurement – solved by many open-source high-quality RISC-V RTL available on github 2) RTL design concepts & architecture understanding – solved by high-quality online tutorials available on https://www.vlsisystemdesign.com/ 3) Industry grade EDA tools – solved by open-source eda tools 4) Guidance on how to use open-source tools – solved by high class tutorial on https://www.vlsisystemdesign.com/ on how to use open-source tools 5) Why would you want to build RISC-V SoC? – Solved by cloud-based revenue sharing technique by VSD.
This marked an end for all back-end related papers.
Next, we started with front-end presentation and Steve Hoover from Redwood EDA gave an extremely concise “Front-end symposium intro”
Steve brought into notice 4 barriers to open-source hardware 1) Access to tools – solved by complete open-source FPGA design flows 2) Access tp hardware – solved using cloud FPGA’s 3) Complexity and scalability – TL-Verilog is the answer 4) Patents – we will get back on this
Steve’s http://makerchip.com/ has in-browser access to tools and solves almost all barriers mentioned above
This presentation was followed by 2 more presentations on TL-Verilog
One by Akos Hadnagy, TU Delft, whose presentation was on “Formal verification on WARP-V”
The goal of WARP-V was flexibility i.e. to leverage and showcase TL-verilog to build the world’s most flexible CPU core IP. Flexibility is tough, as small conceptual variation requires extensive RTL parametrization of staging (flip-flops), stitching through hierarchy, clock gating/enabling and many more. SystemC with HLS is not ideal for CPU’s with tight cycle-level interactions.
The 2 best approaches 1) Macro Preprocessor (M4) provides parametrization, component selection and code generation. 2) Transaction-Level verilog (TL – X.org) implies from context and does staging, stitching through hierarchy and clock gating/enabling.
WARP-V was brought to life using 11-instruction test program and remaining verification was done using formal tools (riscv-formal by Clifford wolf), from early stages of development
Final presentation was from Ahmed Salman, from Alexandria University and his topic was “Top-Down transaction-level design with TL-Verilog”
He talked about top-down design (start design from overall description and end design with smallest detail), timing-abstract circuit design, transaction-level design, lexical re-entrance and generic library (combination flow components, like arbiters)
All papers can be found in below link:
This way, on 27th October, 2018 – the first online VLSI conference was held and all of us.
And, if we become as successful as DAC, in upcoming years, then all presenters and participants at VSDOpen2018 become a part of history