VSDOpen 2018 Keynote & Paper

First ever Online Semiconductor Conference was successfully attended by presenters and audience all over the world from different time zone and made it a grand event. All thanks to the Keynote speakers and  Paper presenter who delivered so advanced industry edge content to our audience.

Please find the presentation by our Keynote Speakers and all selected papers :

Keynote 1 : A New Golden Age for Computer Architecture:History, Challenges, and Opportunities

David Patterson a retired UC Berkeley professor of computer science who joined Google in 2016 to work on computer architectures for machine learning. He is a Turing Award winner, an elected member of the National Academy of Sciences and the National Academy of Engineering, and vice chair of the RISC‑V Foundation.



Keynote 2: Professional Growth with ACM SIGDA 

Xiaobo Sharon Hu is a professor of Computer Science & Engineering and Electrical Engineering at University of Notre Dame, USA. She is a fellow of IEEE. She is an accomplished researcher and also served the community in various roles. She is the current chair of ACM SIGDA.



TAU 2019 Contest Announcement

Dr. George Chen received a bachelor’s of electrical engineering from Caltech and a doctorate degree from Stanford University.  He is the Timing Domain Lead in the Programmable Solutions Group at Intel Corporation.



Paper 1: Padframe Generator for Qflow

Philipp Gühring is a software developer with a strong background in security and cryptography. He is currently learning microelectronics. He has lots of experience developing IT security / cryptographic applications.



Keynote 3: Applying Open community Innovation to hardware Product creation

Mohamed Kassem  is the CTO and Co-Founder of efabless.com, the first semiconductor company applying open community innovation to all aspects of product development. Prior to launching efablesshe held several technical leadership and management positions with Texas Instrument’s Wireless Business Unit. He was responsible for integrated analogIP design from 180nm through 28nm from technology inception to qualified volume production for TI’s mobile phone applications processors OMAP. Mohamed joined Texas Instruments’ Wireless Technology CenterUnit in 2000 as a mixed-signal designer and a key leader in CMOS analogintegration on Wireless SoC’s. He was elected as a Senior Member of Technical Staff in 2006 and held several technical and global leadership posts within TI’s Wireless Business Unit.

Paper 2: PNR for digital core IC to pads using Cloud based eda tool

AnandRajgopalan Completed bachelor’s in Electrnics& Telecomm Enginneringfrom Mumbai University. Microelectronics was my elective subject in one of the semesters. Design & Synthesis of Real time clock in Altera CPLD board . Presently I have took training from VLSI Guru, Bangalore  in Functional Verilog , did some projects based on AXI protocol and memory verification.


Paper 3: Coverage Driven Functional Verification on RISC-V Cores

Lavanya J Project Officer with SHAKTI Group, IIT Madras. Completed MS at IITM and worked in the industry as verification engineer for 7 years.





Anmol Sahoo Project Staff with Shakti. Mechanical engineer from BITS PilaniGoa Campus, really into computer architecture.




Paul George Project Associate IIT MAdrasB.TechShiv Nadar University ,working on Computer Architecture Design and Design Verification.




Paper 4: Rapid Physical Implementation and Integration using eFabless platform

Alberto Gomez Saiz is a Mixed Signal IC Design Engineer with over 5 years of experience in industry. He has been involved the design of SoCs for IoT and connectivity, designing state of the art low power analog IP. Alberto holds a MSc. degree in IC design from Imperial College in London, U.K.




Paper 5: Introduction to TL-Verilog

Steve Hoover is the founder of Redwood EDA. Steve holds a BS in electrical engineering from Rensselaer Polytechnic Institute and an MS in computer science from the University of Illinois. He has designed numerous components for high-performance server CPUs and network architectures for DEC, Compaq, and Intel. Students will learn Transaction-Level Verilog modelingtechniques to generate Verilog models in half the time using the makerchip.comfree online IDE. A new open-source RISC-V CPU development effort will be introduced that showcases flexible IP design practices.

Paper 6: Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator

Akos Hadnagy is a master’s student at TU Delft. He became involved in the WARP-V project through the Google Summer of Code programme this summer. His interest includes heterogeneous and reconfigurable computing, FPGA and hardware development.



Paper 7: Top-Down Transaction-Level Design with TL-Verilog

Ahmed Salman Just graduated from Alexandria University Faculty of Engineering Electronics and communication department, Now working at Intensivate.



Conclusion: Time to productize and monetize your open-source Idea with VSD

 Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt.Ltd. Prior to launching VSD in 2017, Kunal held several technical leadership positions at Qualcomm’s Test-chip business unit. He joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips. At 2013, he joined Cadence as Lead Sales Application engineer for Tempus STA tool. Kunal holds a Masters degree in Electrical Engineering from Indian Institute of Technology (IIT), Bombay, India and specialized in VLSI Design & Nanotechnology.

Anagha Ghosh, Co-Founder VSD and Project Advisor in Microprocessor development MEIT Project to RISE lab, Computer Science & Engineering Dept IIT Madras. She has also worked with TATA Power as Power enggand Project Manager. She is graduated from Mumbai University in Electrical Engineering.