For the upcoming Capture The Bug Hackathon, participant is free to choose any Verilog Open Source design from any website/reference similar to that of OpenCores with appropriate licensing which is compatible with Icarus Verilog and also the Verilog code needs to be synthesizable.
Happy Verification!!!
The working of digital computers, smartphones, etc all have some underlying basic logic manipulating just 0s and 1s to come up with interesting outcomes. With […]
The different projects which we have here are 1) modifying RISC-V core so that it recognizes all these instructions to a vector accelerator 2) vector accelerator itself is decoding vector instructions and managing the execution and retirement of these vector instructions
You might have seen the above image in one form or another, in different our blogs or VSD websites. Every trapezoid in above image is […]
Constant development of tools often breaks something internally which can lead to other issues. Hence there is a need to test the tool for its previous supporting features. But the tool needs an environment to get launched and good test cases to test the features. This is called as “Continuous Integration (CI)”. I
From nothing to Tapeout Ready basic designs – These 7 students have seen it all. Congratulations to all of them. Great start to their semiconductor career.
Here’s the link with their design details-
VSD promises to deliver similar IP design workshops in upcoming days, followed by the next big leap – SoC design workshop with VSD SoC generator using all VSD IPs developed by VSD community using Skywater 130 nm technology node.
Power analysis has materialized as a principal theme in today’s world in semiconductor industries. As very large scale integrated circuit (VLSI) are far beyond from human ability because of complexity in nature. So to analyse power in these circuits we use open source computer aided tools, plenty of tools are available but most of them are costly. I designed an open source power analysis tool for the academic use. This tool gives out values of average and leakage power of any circuit by just giving the netlist of circuit file along with name of supply voltage as input. This tool is designed in python language.
The task given to me was “Design of Open-source Power analysis tool – calculate average switching power and leakage power – Using TCL/Perl/Python – any language”. The entire program is divided into 4 phases.
Above article does talk about chip shortage, which is due to increased demand of consumer electronics like laptops, tablets, mobiles, which was never the case […]
Welcome to the World’s only online conference in Semiconductor Industry VSDOpen Conference. With enormous support and global presence of audience from different segments of industrial lobby and academia made a highly successful event. Evolution is change in the genetic makeup of a population over time, online conference is one kind evaluation everyone adapt soon.
VSD offers online course in complete spectrum of vlsi backend flow from RTL design, synthesis and Verification, SoC planning and design, Sign-off analysis, IP Design, CAD/EDA automation and basic UNIX/IT, Introduction to latest technology – RISC-V, Machine intelligence in EDA/CAD, VLSI Interview FAQ’s.
Current Reach – As of 2021, VSD and its partners have released 41 online VLSI courses and was successfully able to teach ~35900 Unique students around 151 countries in 47 different languages, through its unique info-graphical and technology mediated learning methods.
