CMOS Circuit Design & Spice Simulation using SKY130 Technology

Beginner electronics engineer is introduced to components like BJT from the most famous book by Robert Boylestad. This is the first step towards understanding VLSI Nano-Technology concepts. MOSFET is the second stage and the most important component to learn VLSI Design approach.

Today, 99% of the digital IC market comprises of MOSFET still many experts struggle in field of VLSI design, due to weak MOSFET fundamentals. VLSI Engineers should necessarily require to understand basic MOSFET along with CMOS inverter sizing concepts. Because every field in VLSI, like Physical Design, Static Timing Analysis, Physical Verification, Custom Layout, IP design, Power Analysis, SoC design, Chip planning and many more domains are built on top of MOSFET fundamentals.

This course is designed to cover 90% of NMOS, PMOS and CMOS labs, only for college freshers, serious VLSI job seekers and new college graduates (NCG’s) who really want to make it big in the field of VLSI and nano-technology.

Workshop Day wise Content :

Day1 : Basics of NMOS Drain current (Id) vs Drain-to-source Voltage (Vds)

  • Introduction to Circuit Design and SPICE simulations
    1. Why do we need SPICE simulations?
    2. Introduction to basic element in Circuit design – NMOS
    3. Strong inversion and threshold voltage
    4. Threshold voltage with positive substrate potential
  • NMOS resistive region and saturation region of operation
    1. Resistive region of operation with small drain-source voltage
    2. Drift current theory
    3. Drain current model for linear region of operation
    4. SPICE conclusion to resistive operation
    5. Pinch-off region condition
    6. Drain current model for saturation region of operation
  • Introduction to SPICE
    1. Basic SPICE setup
    2. Circuit description in SPICE syntax
    3. Define technology parameters
    4. First SPICE simulation

Day2 : Velocity saturation and basics of CMOS inverter VTC

  • SPICE simulation for lower nodes and velocity saturation effect
    1. SPICE simulation for lower nodes
    2. Drain current vs gate voltage for long and short channel device
    3. Velocity saturation at lower and higher electric fields
    4. Velocity saturation drain current model
  • CMOS voltage transfer characteristics (VTC)
    1. MOSFET as a switch
    2. Introduction to standard MOS voltage current parameters
    3. PMOS/NMOS drain current v/s drain voltage
    4. Step1 – Convert PMOS gate-source-voltage to Vin
    5. Step2 & Step3 – Convert PMOS and NMOS drain-source-voltage to vout
    6. Step4 – Merge PMOS – NMOS load curves and plot VTC

Day3 : CMOS Switching threshold and dynamic simulations

  • Voltage transfer characteristics – SPICE simulations
    1. SPICE deck creation for CMOS inverter
    2. SPICE simulation for CMOS inverter
  • Static behavior evaluation – CMOS inverter robustness – Switching Threshold
    1. Switching Threshold, Vm
    2. Analytical expression of Vm as a function of (W/L)p and (W/L)n
    3. Analytical expression of (W/L)p and (W/L)n as a function of Vm
    4. Static and dynamic simulation of CMOS inverter
    5. Static and dynamic simulation of CMOS inverter with increased PMOS width
    6. Applications of CMOS inverter in clock network and STA

Day4 : CMOS Noise Margin robustness evaluation

  • Static behavior evaluation – CMOS inverter robustness – Noise margin
    1. Introduction to noise margin
    2. Noise margin voltage parameters
    3. Noise margin equation and summary
    4. Noise margin variation with respect to PMOS width

Day5 : CMOS power supply and device variation robustness evaluation

  • Static behavior evaluation – CMOS inverter robustness – Power supply variation
    1. Smart SPICE simulation for power supply variations
    2. Advantages and disadvantages using low supply voltage
  • Static behavior evaluation – CMOS inverter robustness – Device variation
    1. Sources of variation – Etching process
    2. Sources of variation – oxide thickness
    3. Smart SPICE simulation for device variations
    4. Conclusion

Refund Policy:

  1. Last date to apply for refund is 15 February 2021 11:59 PM IST.
  2. Students absent during Workshop NOT eligible for Refund.

Format: Cloud based Virtual Training Workshop

Duration – 5 Day

Cost : $70

Date :  17-21 February 2021

Last date for Registration:

15 February 2021 11:59 PM IST

Refund Policy:

Last date to apply for refund is 15 February 2021 11:59 PM IST.

Students absent during Workshop NOT eligible for Refund.

Registration : 

CLOSED

For Information drop email :

vsd@vlsisystemdesign.com