Day1:
- Introduction to FPGA
- Counter example using Vivado
- Counter Verilog explanation and implementation using Vivado
- Vivado timing, power, and area measurement for counter
- Introduction to VIO
Day2:
- Introduction to OpenFPGA and VTR (verilog-to-routing)
- Introduction to VPR (versatile-place-and-route) using basic Earch fabric
- Counter example using VPR/VTR openfpga flow
Day3:
- Introduction to basic RISC-V core – rvmyth
- Rvmyth – Vivado RTL to synthesis flow
- Rvmyth – Vivado Synthesis to bitstream
Day4:
- Introduction to opensource SOFA FPGA fabric
- Steps to run counter example on SOFA
- Characterize counter example in terms of area and timing
- Post-implementation netlist and simulation using SOFA
Day5:
- Steps to run RISC-V Core - on SOFA
- Characterize RVmyth in terms of performance and area
- Steps to generate rvmyth post-implementation netlist
- Confirm RVmyth on SOFA behavioral simulation using Vivado
Xilinx Basys3
- Virtual Coach platform with expert instructor guidance
- Cloud-based dedicated Virtual Machine to perform Design labs
- Intelligent Assessment Technology (IAT) and Project allocation
- 24 hours Lab access for 5 days and Instructor assistance on demand
Dr. Nanditha Rao is an Assistant Professor in the VLSI Systems group at IIIT Bangalore. She obtained her PhD in Electrical Engineering from IIT, Bombay in 2017. Her current research interests are in the area of processor architecture, RISC-V based designs, FPGA based designs, FPGA based acceleration of neural networks and radiation tolerant/hardened designs. Prior to joining for PhD, she worked as a Hardware design engineer (mainly Signal Integrity) at Intel Technologies, Bangalore for a period of 5+ years. At Intel, she was mainly responsible for signal integrity simulations of motherboard interconnects for high-speed differential interfaces such as pci-express, LVDS, DisplayPort, HDMI and so on. She interacted with customers in the Asia Pacific region on motherboard design guidelines and specialized in buffer modeling.
Are there any prerequisites for the workshop?
Basic knowledge of digital design and electronics.
Can VLSI freshers join this workshop?
Yes, it will be very helpful for VLSI freshers as they can learn about the Open-source FPGA fabric, design and architecture , which will enable them to explore this field on their own and learn. So as long as you are looking forward to learning something new and making a bright career in the field of VLSI, you are welcome.The workshop is designed in such a way that, we start with the basics first and then move on to advanced concepts. Have a look at curriculum in above registration link.
Is this workshop also for experienced VLSI engineers?
Yes, If you are an experienced VLSI professional and want to learn about the OpenFPGA Fabric design, you are welcome to join this workshop.
Is there any certification provided for the participants?
Yes, Each participant with a completed Github repo will receive a certificate with performance score.
Refund Policy: https://www.vlsisystemdesign.com/terms-and-conditions/
Refund Policy: If you are not able to join workshop, last date to apply for refund in 21 March 2022 11:59 PM IST
For Term & Condition Policy: https://www.vlsisystemdesign.com/terms-and-conditions/