The RISC-V Edge AI Internship is a four-week, task-driven program built around the SiFive FE310-G002–based VSDSquadron Pro. It combines the complete 10-day RISC-V Edge AI workshop with six progressive internship tasks, producing a continuous 28-day path from machine-learning foundations to live, on-device inference.
During the first 10 days, you build the technical base: understand the board and its memory constraints, move from regression to classification, explore MNIST digit recognition, study quantization, and understand the Python-to-embedded-C path. During the next 18 days, you execute six three-day engineering tasks covering board bring-up, model training, optimization, firmware deployment, UART streaming, timing analysis, and a webcam-to-RISC-V capstone.
The work is deliberately hardware-aware. You will evaluate accuracy against model size, account for the board’s 16 KB data SRAM constraint, use integer or fixed-point techniques where appropriate, and document the difference between a model that merely trains and a system that reliably runs.
The internship follows one continuous engineering pipeline. You begin with a known-good board and toolchain, train a compact digit-recognition model, optimize it for the available memory, export its parameters to C, deploy the inference firmware, stream new images over UART, measure real performance, and finally connect a webcam to the complete system.
End-to-end flow
Dataset → Training → Evaluation → Quantization → C model export → RISC-V firmware → VSDSquadron Pro → UART input/output → Latency analysis → Live capstone
A Complete Open, Reproducible Edge AI Workflow
This is a submission-based internship. Completion should reflect demonstrated work, not passive attendance. A participant is considered to have completed the program after submitting all six task folders, documenting the 10-day foundation work, showing successful physical-board inference, presenting measured performance results, and completing the capstone demonstration.
Suggested completion gate All mandatory tasks submitted GitHub repository is reproducible Physical-board UART inference is demonstrated Latency results are reported Capstone demo and final README are complete |
You do not need prior TinyML or advanced RISC-V experience. You should, however, be comfortable learning by building and documenting work every day. Basic Python programming—variables, loops, functions, arrays—and basic algebra are expected. Familiarity with machine-learning concepts, C programming, Linux commands, Git, or microcontrollers is helpful but can be developed during the program.
You will need a laptop, a stable internet connection, a GitHub account, and access to the VSDSquadron Pro hardware for the physical deployment tasks. The most important requirement is the discipline to run experiments, debug failures, maintain evidence, and complete the full 28-day submission path.
After completing the internship, you should be able to explain—using your own code and results—how a model moves from Python training to quantized parameters, embedded C, RISC-V execution, live data transfer, and measured inference. You should be able to discuss why you selected a particular architecture, what it costs in memory, how inputs are framed and preprocessed, and where system latency is spent.
The program is designed to build demonstrable capability for entry-level work and further projects in Edge AI, TinyML, embedded systems, intelligent IoT, RISC-V software, firmware development, and hardware-aware ML. It does not guarantee a job. It gives you the technical proof and vocabulary needed to compete more credibly for relevant opportunities.
No advanced experience is required. Basic Python and algebra are enough to begin. The 10-day foundation introduces the progression from regression and classification to neural networks, quantization, and embedded deployment. You must be prepared to study code, run experiments, and document your results.
Prior exposure is helpful but not mandatory. The first internship task validates the toolchain, flashing workflow, UART, and board operation before AI deployment begins. Basic C familiarity will make the later firmware tasks easier.
Yes. The core differentiator is deployment on the VSDSquadron Pro. Simulation and desktop training support development, but the internship’s physical evidence includes flashing firmware, running inference, observing UART output, and validating live data on the board.
The checkout page must clearly state the current board-inclusion, shipping, and replacement policy. The VSDSquadron Pro is required for the physical deployment and capstone tasks; participants should confirm the applicable hardware arrangement before enrolling.
The primary internship path uses handwritten-digit recognition because it provides a compact, measurable pipeline from 28×28 input through model training, quantization, embedded inference, UART transfer, and webcam capture. The final task also asks you to adapt the workflow to a related classification problem.
A normal course may stop at training accuracy or a notebook demonstration. This program continues into model size, RAM feasibility, C export, RISC-V firmware, physical-board execution, UART input, robustness testing, latency measurement, and a live capstone.
Evaluation is evidence-based. Your repository should show working code, build and flash commands, experimental comparisons, model artifacts, hardware logs, UART results, performance measurements, troubleshooting notes, and the final demonstration. Completion depends on submissions, not attendance alone.
You can walk through one coherent engineering story: dataset and architecture selection, accuracy-versus-memory experiments, quantization, embedded-C integration, RISC-V execution, UART protocol design, measured latency, and a webcam-to-board demo—with proof in your repository.
A completion certificate can be issued to participants who satisfy the stated submission and demonstration requirements. The stronger outcome is the reproducible technical portfolio created during the 28-day program.
No. The internship is designed to build credible, demonstrable skills for Edge AI, TinyML, firmware, RISC-V, intelligent IoT, and embedded roles. Selection decisions remain with employers and project owners.
VSD, standing as a trailblazing Semiconductor EdTech company and a community-based Technology Aggregator, is revolutionizing the landscape of VLSI Design. With the belief that “Creativity is just connecting things”, VSD has mastered the art of linking the right resources with the community. This unique approach has sparked a significant transformation in the VLSI Design process.
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The “Ethical RISC-V IoT Workshop” at IIIT Bangalore, organized in collaboration with VSD, is a structured, educational competition aimed at exploring real-world challenges in IoT and embedded systems. Participants progress through three stages: building an application, injecting and managing faults, and enhancing application security. The event spans from May 9 to June 15, 2024, culminating in a showcase of top innovations and an award ceremony. This hands-on hackathon emphasizes learning, testing, and securing applications in a collaborative and competitive environment.
Welcome to the World’s only online conference in Semiconductor Industry VSDOpen Conference. With enormous support and global presence of audience from different segments of industrial lobby and academia made a highly successful event. Evolution is change in the genetic makeup of a population over time, online conference is one kind evaluation everyone adapt soon.
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