This 10-day workshop trains participants in tapeout-ready physical verification using the SkyWater SKY130 PDK and open-source EDA tools. It begins with SKY130 fundamentals, PDK layers, devices, libraries, Xschem, Magic, ngspice and basic DRC/LVS flow. Participants then learn GDS handling, layout extraction, DRC rule setup, LVS setup and XOR checks. The workshop covers front-end and back-end DRC rules, antenna, latch-up, density and ERC concepts, followed by OpenLANE-based RTL-to-GDS PNR, DRC fixing, Netgen LVS debugging, hierarchy, blackboxes, macros, standard cells and analog/digital block verification labs.
This 10-day workshop introduces participants to physical verification for tapeout readiness using the SkyWater SKY130 PDK and open-source EDA tools. It covers the complete post-layout verification mindset, beginning with SKY130 layers, devices, libraries, Xschem, Magic, ngspice, GDS handling, layout extraction, DRC setup, LVS setup, and XOR checks.
Participants then move into deeper tapeout-related checks including front-end and back-end DRC rules, antenna effects, latch-up, density rules, ERC concepts, and hierarchical verification. The workshop also includes OpenLANE-based RTL-to-GDS PNR, DRC fixing, Netgen LVS debugging, blackbox and macro handling, standard-cell verification, and analog/digital block verification labs, helping learners understand how layouts are validated before final tapeout submission.
Kunal Ghosh, the visionary co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd., stands at the forefront of online open-source EDA and hardware design education, particularly in the realm of RISC-V.
With a portfolio of 50 top-tier VLSI online courses, Kunal has enriched the learning journey of over 90,000 students across 153 countries. His expertise extends beyond training; he’s actively involved in pioneering open-source projects and design collaborations with esteemed institutions like IIT Madras, IIT Bombay, IIT Guwahati and IIT Hyderabad.
His current focus is on crafting high-quality open-source Analog/Digital IPs, a groundbreaking endeavor in open-source hardware design. Kunal’s rich industry experience includes roles at Qualcomm and Cadence, specializing in SoC design. He holds a master’s degree from IIT Bombay, where he specialized in VLSI & Nano-electronics, with a focus on sub-100nm Electron Beam Lithography Optimization techniques.
Tim Edwards is a leading open-source silicon advocate and one of the most respected contributors to the open-source EDA ecosystem. He has worked extensively on tools such as Magic, Netgen, and open_pdks, and has contributed significantly to open PDK development including SKY130 and GF180MCU. His deep experience in analog design, layout, DRC/LVS flows, and tapeout infrastructure makes him an ideal instructor for this workshop on Physical Verification for Tapeout Readiness using SKY130.
Yes. The workshop runs on a cloud-hosted platform, so you can log in whenever it suits you, watch the day’s lectures, complete the physical verification labs, and log out. Mentor support will be available through the workshop support channel to help with tool issues, DRC/LVS debugging and lab submissions during the program window.
Yes. This workshop is designed to be fresher-friendly. If you understand basic electronics, CMOS inverter, simple logic gates, schematic and layout concepts, you can follow the flow. The labs are structured step by step so that students and fresh graduates can learn DRC, LVS, extraction and GDS verification from the foundation level.
Yes. The workshop starts with SKY130 PDK basics, layout layers, devices, rule files and tool usage before moving into DRC, LVS, extraction, antenna, density and GDS checks. With basic VLSI awareness and willingness to perform hands-on labs, you should be able to complete the exercises with guided support.
Absolutely. Engineers working in physical design, layout, analog/mixed-signal design or open-source chip design can use this workshop to strengthen their understanding of tapeout-readiness checks. The workshop covers practical debugging of DRC errors, LVS mismatches, extraction issues, hierarchy problems, GDS inspection and layout sign-off concepts using SKY130.
No. The workshop uses a pre-configured cloud lab environment with the required SKY130 PDK and tools such as Magic, Netgen, Xschem, ngspice, KLayout and selected OpenROAD/OpenLANE flows. This helps participants start quickly without spending time on local installation and tool setup issues.
You will work mainly with Magic for layout, DRC and extraction; Netgen for LVS; Xschem for schematic and netlist generation; ngspice for simulation; and KLayout for GDS viewing and hierarchy inspection. Selected labs may also use OpenROAD/OpenLANE to understand routed digital layouts and verification issues.
No. This is not a functional verification or RTL testbench workshop. It focuses on physical verification after schematic, layout or routing. The main topics are DRC, LVS, extraction, GDS inspection, antenna, density, ERC concepts and tapeout-readiness checks.
Before a layout can move towards tapeout, it must pass important physical verification checks. This workshop teaches how layouts are checked for manufacturability, connectivity correctness and final GDS readiness. Participants learn why DRC, LVS, extraction, hierarchy and GDS checks are critical before final chip submission.
Workshop videos, notes, lab manuals and required files will be available during the workshop window. Since this is a structured, industry-oriented sprint, lab submissions and report completion should be done within the given workshop duration to qualify for certification.
Participants will submit lab reports containing DRC results, LVS results, extraction outputs, GDS screenshots, debugging observations and verification summaries. This final documentation can become a strong portfolio artifact for layout, physical design, analog/mixed-signal and open-source chip design roles.
Physical verification is one of the most important steps before tapeout. A design is not complete just because the schematic works or the layout is drawn. It must pass DRC, LVS, extraction and other manufacturability checks. This workshop helps participants build practical skills that are directly useful in layout, physical design, sign-off and tapeout-oriented VLSI roles.
Yes. Participants who complete the required labs and submit the workshop report within the program timeline will receive a VSD certificate. The certificate, along with the lab report and screenshots, can be used as evidence of hands-on physical verification experience.
Cloud based Workshop
VSD, standing as a trailblazing Semiconductor EdTech company and a community-based Technology Aggregator, is revolutionizing the landscape of VLSI Design. With the belief that “Creativity is just connecting things”, VSD has mastered the art of linking the right resources with the community. This unique approach has sparked a significant transformation in the VLSI Design process.
Over the past decade, VSD has made remarkable strides in the open-source semiconductor domain. Our journey includes the development of comprehensive training content, empowering students to design silicon-grade IP/SoC. Notably, we’ve successfully guided these projects through the tapeout cycle via the Google open shuttle program. This achievement is a testament to our commitment to hands-on, practical education.
At VSD, our role extends beyond traditional education. While we didn’t invent EDA tools or design flows, we’ve made them accessible to a wider community. Our mentorship has been instrumental in the development of over 50+ Analog/Digital IPs and solutions. Impressively, 20+ of these have successfully transitioned from concept to Silicon – a clear indicator of our effective approach and the high quality of work produced under our guidance.
We pride ourselves on fostering a community-based revolution in the Semiconductor Industry. By democratizing access to advanced tools and knowledge, VSD is not just educating individuals; we are building a community of innovators poised to lead the next wave of advancements in the semiconductor sector. With VSD, the future of VLSI Design is not just being written; it’s being rewritten by a passionate and empowered community.
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The “Ethical RISC-V IoT Workshop” at IIIT Bangalore, organized in collaboration with VSD, is a structured, educational competition aimed at exploring real-world challenges in IoT and embedded systems. Participants progress through three stages: building an application, injecting and managing faults, and enhancing application security. The event spans from May 9 to June 15, 2024, culminating in a showcase of top innovations and an award ceremony. This hands-on hackathon emphasizes learning, testing, and securing applications in a collaborative and competitive environment.
Welcome to the World’s only online conference in Semiconductor Industry VSDOpen Conference. With enormous support and global presence of audience from different segments of industrial lobby and academia made a highly successful event. Evolution is change in the genetic makeup of a population over time, online conference is one kind evaluation everyone adapt soon.
VSD offers online course in complete spectrum of vlsi backend flow from RTL design, synthesis and Verification, SoC planning and design, Sign-off analysis, IP Design, CAD/EDA automation and basic UNIX/IT, Introduction to latest technology – RISC-V, Machine intelligence in EDA/CAD, VLSI Interview FAQ’s.
Current Reach – As of 2021, VSD and its partners have released 41 online VLSI courses and was successfully able to teach ~35900 Unique students around 151 countries in 47 different languages, through its unique info-graphical and technology mediated learning methods.
