RISC-V based MYTH (Microprocessor for You in Thirty Hours)

A beginner level 5-day workshop on “RISC-V based MYTH”  (24hrs x 5days on VSD-IAT platform)

When we say, “beginner level”, by end of workshop you will understand
• RISC-V specs
• RISC-V software
• How to implement RISC-V basic specs using TL-Verilog
• Simulate your own RISC-V core
*In short, you are going to write RTL and build RISC-V core on your own*

Workshop Day wise Content :

Day 1 : Introduction to RISC-V ISA and GNU compiler toolchain

  1. Introduction to RISC-V basic keywords
  2. Labwork for RISC-V software toolchain
  3. Integer number representation
  4. Signed and unsigned arithmetic operations
Day 2: Introduction to ABI and basic verification flow
  1. Application Binary interface (ABI)
  2. Lab work using ABI function calls
  3. Basic verification flow using iverilog

Day 3: Digital Logic with TL-Verilog and Makerchip

  1. Combinational logic in TL-Verilog using Makerchip
  2. Sequential and pipelined logic
  3. Validity
  4. Hierarchy

Day 4: Basic RISC-V CPU micro-architecture

  1. Microarchitecture and testbench for a simple RISC-V CPU
  2. Fetch, decode, and execute logic
  3. RISC-V control logic

Day 5: Complete Pipelined RISC-V CPU micro-architecture/store

  1. Pipelining the CPU
  2. Load and store instructions and memory
  3. Completing the RISC-V CPU
  4. Wrap-up and future opportunities

Many people have been asking VSD for a workshop on how to do RTL coding – Well, there you go.

Refund Policy:

  1. Last date to apply for refund is 22 March  2021 11:59 PM IST.
  2. Students absent during Workshop NOT eligible for Refund.

Format

Cloud based Virtual Training Workshop

Duration - 5 Days ( +2 day support) 

Cost -  $199 $70

Date : 24-28 March 2021

Last date for Registration: 22 March 2021

Refund Policy:

  1. Last date to apply for refund is 22 March  2021 11:59 PM IST.
  2. Students absent during Workshop NOT eligible for Refund.

Registration: CLOSED

For Information drop email : vsd@vlsisystemdesign.com