
RISC-V based MYTH (Microprocessor for You in Thirty Hours)
A beginner level 5-day workshop on “RISC-V based MYTH” (24hrs x 5days on VSD-IAT platform)
When we say, “beginner level”, by end of workshop you will understand
• RISC-V specs
• RISC-V software
• How to implement RISC-V basic specs using TL-Verilog
• Simulate your own RISC-V core
*In short, you are going to write RTL and build RISC-V core on your own*
Workshop Day wise Content :
Day 1 : Introduction to RISC-V ISA and GNU compiler toolchain
- Introduction to RISC-V basic keywords
- Labwork for RISC-V software toolchain
- Integer number representation
- Signed and unsigned arithmetic operations
- Application Binary interface (ABI)
- Lab work using ABI function calls
- Basic verification flow using iverilog
Day 3: Digital Logic with TL-Verilog and Makerchip
- Combinational logic in TL-Verilog using Makerchip
- Sequential and pipelined logic
- Validity
- Hierarchy
Day 4: Basic RISC-V CPU micro-architecture
- Microarchitecture and testbench for a simple RISC-V CPU
- Fetch, decode, and execute logic
- RISC-V control logic
Day 5: Complete Pipelined RISC-V CPU micro-architecture/store
- Pipelining the CPU
- Load and store instructions and memory
- Completing the RISC-V CPU
- Wrap-up and future opportunities
Many people have been asking VSD for a workshop on how to do RTL coding – Well, there you go.
Refund Policy:
- Last date to apply for refund is 30 November 2020.
- Students absent during Workshop NOT eligible for Refund.
- RISC-V ISA Simulator
- RISC-V GNU Tool-chain
- Spike
- TL-Verilog
- Markerchip IDE
Refund Policy:
- Last date to apply for refund is 30 November 2020.
- Students absent during Workshop NOT eligible for Refund.
- Virtual Coach platform with expert instructor guidance
- Cloud-based dedicated Virtual Machine to perform Design labs
- Intelligent Assessment Technology (IAT) and Project allocation
- 24 hours Lab access for 5 days and Instructor assistance on demand
- Simulate basic C program using RISC-V ISA simulator, debug using Spike - all on VSD-IAT platform
- Design own RISC-V core using TL-Verilog and verify using verilator - all on Makerchip IDE
Refund Policy:
- Last date to apply for refund is 30 November 2020.
- Students absent during Workshop NOT eligible for Refund.
Instructor Profile:
Kunal Ghosh, co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd., Kunal pioneers in the field of online open-source EDA (qflow & openroad)/open-source hardware (specially RISC-V) design and learning. Currently, Kunal owns around 32 high-quality VLSI online courses in and around open-source EDA/hardware, which is being consumed by around 28700+ students around 141 countries. Apart from trainings, Kunal has also worked with IIT Madras and IIT Guwahati on open-source activities and design projects. Currently, Kunal and his team are working on developing high quality open-source Analog/Digital IP’s which would be first one’s in the field of open-source hardware design. Prior to VSD, Kunal has worked with Qualcomm and Cadence, in field of SoC design. Kunal has done his Masters at IIT Bombay in field of VLSI & Nano-electronics, with specialisation in Sub-100nm Electron Beam LithographyOptimisation techniques
Steve Hoover, founder of Redwood EDA, Steve is fostering an open-source silicon ecosystem through numerous technologies including the WARP-V CPU core generator with support for RISC-V. His main focus is design methodology and tools enabled by Transaction-Level Verilog (TL-Verilog), available to all at makerchip.com. He is also the lead developer of the 1st CLaaS open-source framework for cloud FPGAs. Steve holds a BS in electrical engineering summa cum laude from Rensselaer Polytechnic Institute and an MS in computer science from the University of Illinois. He has designed numerous components for high-performance server CPUs and network architectures for DEC, Compaq, and Intel.
Format
Cloud based Virtual Training Workshop
Duration - 5 Days ( +2 day support)
Cost - $199 $59
Date : 2-6 December 2020
Last date for Registration: 30 November 2020
Registration:
Indian Student
International Student