Workshop intends to teach the verilog coding guidelines that results in predictable logic in Silicon. it is important to note that every verilog code is not synthesizable and even if it is , it may result in different logic depending on the coding styles used. The course details all these aspects of the Verilog HDL with theory and backed with lot of practical examples. Workshop introduces to the digital logic design using Verilog HDL . Validating the functionality of the design using Functional Simulation. Writing Test Benches to validate the functionality of the RTL design . Logic synthesis of the Functional RTL Code. Gate Level Simulation of the Synthesized Netlist.

Workshop Day wise Content :

Day 1 - Introduction to Verilog RTL design and Synthesis

• Introduction to open-source simulator iverilog
• Labs using iverilog and gtkwave
• Introduction to Yosys and Logic synthesis
• Labs using Yosys and Sky130 PDKs

Day 2 - Timing libs, hierarchical vs flat synthesis and efficient flop coding styles

• Introduction to timing .libs
• Hierarchical vs Flat Synthesis
• Various Flop Coding Styles and optimization

Day 3 - Combinational and sequential optmizations

• Introduction to optimizations
• Combinational logic optimizations
• Sequential logic optimizations
• Sequential optimzations for unused outputs

Day 4 - GLS, blocking vs non-blocking and Synthesis-Simulation mismatch

• GLS, Synthesis-Simulation mismatch and Blocking/Non-blocking statements
• Labs on GLS and Synthesis-Simulation Mismatch
• Labs on synth-sim mismatch for blocking statement

Day 5 - Optimization in synthesis

• If Case constructs
• Labs on "Incomplete If Case"
• Labs on "Incomplete overlapping Case"
• for loop and for generate
• Labs on "for loop" and "for generate"

1. Verilog : Simulator . Used for RTL Simulation and Gate Level Simulations
2. yosys : Opensource Logic Synthesis Tool
3. Skywater 130nm Standard Cell Libraries

1. Virtual Coach platform with expert instructor guidance
2. Cloud-based dedicated Virtual Machine to perform Design labs
3. Intelligent Assessment Technology (IAT) and Project allocation
4. 24 hours Lab access for 5 days and Instructor assistance on demand
5. Run EDA scripts, evaluate VLSI layout and Timing analysis reports on platform

Instructor Profile:

Kunal Ghosh, co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd., Kunal pioneers in the field of online open-source EDA (qflow & openroad)/open-source hardware (specially RISC-V) design and learning. Currently, Kunal owns around 32 high-quality VLSI online courses in and around open-source EDA/hardware, which is being consumed by around 28700+ students around 141 countries. Apart from trainings, Kunal has also worked with IIT Madras and IIT Guwahati on open-source activities and design projects. Currently, Kunal and his team are working on developing high quality open-source Analog/Digital IP’s which would be first one’s in the field of open-source hardware design. Prior to VSD, Kunal has worked with Qualcomm and Cadence, in field of SoC design. Kunal has done his Masters at IIT Bombay in field of VLSI & Nano-electronics, with specialisation in Sub-100nm Electron Beam LithographyOptimisation techniques.

Teaching Assistant Profile:

Shon Taware has completed his post-graduate study in Embedded System and VLSI Design. He has worked on multiple digital RTL design and physical design projects. He has a good understanding of CMOS technology, digital electronics, RTL Design, Synthesis and Static Timing Analysis. He is currently working on a RISC-V project focusing on complete RTL design and open-source RTL to GDS flow.

• What are the prerequisites for taking the course ?
  • Basic knowledge of Digital design is required. Familiarity with Linux OS and Verilog HDL will be an add-on.
• I am a 2nd year engineering student. Can I join this workshop?
  • In our last RISC-V workshop, we had students as young as 8th Grade. So as long as you are looking forward to learning something new and making a bright career in the field of VLSI, you are welcome. This workshop, is kept at a very very basic level, where we make sure basics are covered first. Look at curriculum in above registration link
• Can experienced system designers join for refreshing concepts?
  • We would suggest you to refrain from joining this workshop, as it's especially designed only for freshers looking to start in the field of      VLSI. But, if you are looking to share your RTL Design and Synthesis experience with students, then you are more than welcome to join

• Can I access content after Workshop is finished ?
  • You will be given lifetime access to all lab files after the workshop. Access to videos and VSD-IAT platform will terminate on last day of Workshop
• Do I need to install any software or tools to do labs?
  • No. Labs will be done on VSD-IAT cloud platform. You will be given access to a Linux Terminal, which has all necessary tools installed. Post workshop, we will provide scripts to install all tools on your laptops so you can do all experiments on your laptop and revise
• Will I receive the participation certificate?
  • Yes, every participant will receive certificates with the lab performance score and GitHub repo link.