RTL design using Verilog with SKY130 Technology
Workshop intends to teach the verilog coding guidelines that results in predictable logic in Silicon. it is important to note that every verilog code is not synthesizable and even if it is , it may result in different logic depending on the coding styles used. The course details all these aspects of the Verilog HDL with theory and backed with lot of practical examples. Workshop introduces to the digital logic design using Verilog HDL . Validating the functionality of the design using Functional Simulation. Writing Test Benches to validate the functionality of the RTL design . Logic synthesis of the Functional RTL Code. Gate Level Simulation of the Synthesized Netlist.
Workshop Day wise Content :
Day 1 - Introduction to Verilog RTL design and Synthesis
- Introduction to open-source simulator iverilog
- Labs using iverilog and gtkwave
- Introduction to Yosys and Logic synthesis
- Labs using Yosys and Sky130 PDKs
Day 2 - Timing libs, hierarchical vs flat synthesis and efficient flop coding styles
- Introduction to timing .libs
- Hierarchical vs Flat Synthesis
- Various Flop Coding Styles and optimization
Day 3 - Combinational and sequential optmizations
- Introduction to optimizations
- Combinational logic optimizations
- Sequential logic optimizations
- Sequential optimzations for unused outputs
Day 4 - GLS, blocking vs non-blocking and Synthesis-Simulation mismatch
- GLS, Synthesis-Simulation mismatch and Blocking/Non-blocking statements
- Labs on GLS and Synthesis-Simulation Mismatch
- Labs on synth-sim mismatch for blocking statement
Day 5 - Optimization in synthesis
- If Case constructs
- Labs on "Incomplete If Case"
- Labs on "Incomplete overlapping Case"
- for loop and for generate
- Labs on "for loop" and "for generate"
- Last date to apply for refund is 22 June 2021 11:59 PM IST.
- Students absent during Workshop NOT eligible for Refund.