Day 1: Introduction to TCL and VSDSYNTH Toolbox Usage

Section 1: Introduction

• Lecture 1: Introduction to TCL task
• Lecture 2: Introduction to sub-task

Section 2: Sub-Task One: VSDSYNTH Toolbox usage scenarios

• Lecture 3: Scenario 1 - User doesn't provide an input CSV file
• Lecture 4: Scenarios 2 & 3 - User providing incorrect CSV or typing "-help"

Day 2: Variable Creation and Processing Constraints from CSV

Section 3: Sub-Task Two - From CSV to format[1] and SDC - Variable Creation

• Lecture 5: Various tasks involved in format conversion
• Lecture 7: Auto-Create variables using matrix and arrays
• Lecture 8: Initialize variables for auto-creation variables task
• Lecture 9: Auto creation of the first variable - DesignName
• Lecture 10: Auto creation of variables complete
• Lecture 11: Variable Creation DEMO using TCL

Section 4: Sub-Task Two - From CSV to format[1] and SDC - Processing constraints, CSV

• Lecture 12: Checking the existence of files and folders mentioned in design_details.csv
• Lecture 13: Convert constraints.csv file to a matrix object
• Lecture 14: Compute row number using complex matrix processing
• Lecture 15: DEMO for computing row numbers

Day 3: Processing Clock and Input Constraints

Section 5: Sub-Task Two - From CSV to format[1] and SDC - Processing clock constraints

• Lecture 16: Algorithm to identify the column number for clock latency constraints
• Lecture 17: Start writing clock latency constraints in the SDC file
• Lecture 18: Complete clock latency constraints and clock slew constraints in the SDC file
• Lecture 19: Code to create clock constraints with clock period and duty cycle
• Lecture 20: DEMO for creating complete clock constraints

Section 6: Sub-Task Two - From CSV to format[1] and SDC - Processing input constraints

• Lecture 21: Introduction to the task of differentiating between bits and a bus
• Lecture 22: Algorithm to categorize input ports as bits and bussed
• Lecture 23: File access and pattern creation steps
• Lecture 24: Regular expression and regular substitute to get fixed space strings
• Lecture 25: Demo for grepping input ports from all verilogs and reformatting for fixed space
• Lecture 26: Read, split, uniquify, sort, and join input ports to remove duplication
• Lecture 27: Evaluate the length of the string and Demo of bits/bussed differentiation script
• Lecture 28: Demo for input constraints generation and bits/bussed differentiation

Day 4: Complete Scripting and Yosys Synthesis Introduction

Section 7: Full script for download and Conclusion

• Lecture 29: Constraints generation logic for the output port and Conclusion!!

Section 8: Introduction to Yosys synthesis tool usage

• Lecture 2: Example of a memory module RTL description
• Lecture 3: Memory functionality and Synthesis using Yosys
• Lecture 4: Components and Gate level netlist description of Synthesized memory
• Lecture 5: Memory Write operation discussed in detail
• Lecture 6: Memory Read operation and TCL scripting agenda

Section 9: Hierarchy check and error handling script creation for Yosys

• Lecture 7: Script to do a hierarchy check
• Lecture 8: Demo for hierarchy check script generation
• Lecture 9: Demo for error handling concept in hierarchy check
• Lecture 10: Error handling script for hierarchy check
• Lecture 11: Demo for error handling script

Day 5: Advanced Scripting Techniques and Quality of Results Generation

Section 10: Synthesis main file scripting and output file editing

• Lecture 12: Synthesis script creation and demo
• Lecture 13: Need and script to edit Yosys output netlist
• Lecture 14: Demo to edit output netlist and Introduction to 'procs'

Section 11: World of 'Procs'

• Lecture 15: Redirect stdout proc and demo of TCL array command
• Lecture 16: 'set_multi_cpu_usage' proc
• Lecture 17: Demo for 'set_multi_cpu_usage' proc
• Lecture 18: read_lib and read_verilog proc demo

Section 12: read_sdc proc - interpret clock generation constraints

• Lecture 19: Read SDC file and replace square brackets by 'null'
• Lecture 20: Evaluate clock period and clock port name from processed SDC
• Lecture 21: Evaluate duty cycle and create clock in opentimer format
• Lecture 22: Demo to convert constraints from SDC format to opentimer format

Section 13: read_sdc proc - interpret IO delays and transition constraints

• Lecture 23: Grep clock latency and port name from SDC file
• Lecture 24: Convert set_clock_latency SDC to opentimer format
• Lecture 25: Demo to convert set_clock_latency in SDC to arrival_time in opentimer
• Lecture 26: Script and demo convert transition and input delay to opentimer format
• Lecture 27: Script and demo to convert output SDC constraints to opentimer format

Section 14: Process bussed ports and configuration file creation

• Lecture 28: Script to expand bussed input ports for arrival time constraints
• Lecture 29: Script and demo to convert all bussed constraints to bit-blasted
• Lecture 30: Opentimer configuration file creation

Section 15: Quality of results (QOR) generation algorithm

• Lecture 31: Script to obtain STA runtime
• Lecture 32: Script to obtain WNS and FEP for reg2out violations
• Lecture 33: Script and demo for instance count, WNS, and FEP for setup and hold
• Lecture 34: Script and demo for report formatting

Section 16: Conclusion

• Lecture 35: Conclusion and acknowledgments

• Yosys
• OpenTimer
• TCL development suite
• Libraries (associated with TCL)

1. Virtual Coach platform with expert instructor guidance
2. Virtual Disk Image to perform Design labs
3. Intelligent Assessment Technology (IAT) and Project allocation
4. 24 hours Lab access for 5 days and Instructor assistance on demand

Kunal Ghosh is a prominent figure in the field of VLSI (Very Large Scale Integration) and open-source hardware design. As the co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd., he has been instrumental in pioneering online open-source EDA and hardware learning. With a focus on tools like qflow and openroad, as well as open-source hardware, particularly RISC-V, Kunal has developed 32 high-quality VLSI online courses that have been widely embraced by over 90,000 students from 153 countries. His expertise and knowledge have made a significant impact on the global VLSI community.

In addition to his online courses, Kunal Ghosh has been actively involved in open-source activities and design projects with prestigious institutions like IIT Madras and IIT Guwahati. This collaboration has further solidified his position as a leading expert in the field. Currently, Kunal and his team are focused on developing high-quality open-source Analog/Digital IP, aiming to contribute groundbreaking designs to the world of open-source hardware. This endeavor demonstrates his commitment to pushing the boundaries of innovation and accessibility in the field.

Kunal Ghosh's professional journey includes valuable experience gained from working with industry giants like Qualcomm and Cadence, where he honed his skills in SoC design. His academic background includes a Master's degree from IIT Bombay, specializing in VLSI and Nano-electronics. Notably, he has conducted research on Sub-100nm Electron Beam Lithography Optimization techniques, showcasing his dedication to pushing the limits of VLSI technology. With a remarkable blend of industry experience, academic achievements, and a passion for open-source hardware, Kunal Ghosh continues to make a significant impact on the VLSI and EDA community.

Teaching Assistant Profile:

Geetima Kachari

Geetima Kachari is an accomplished Assistant Professor at NITS Mirza, specializing in Electronics and Communication Engineering. With a passion for teaching, she has been actively involved in delivering courses and mentoring B.Tech final year students in their projects. Her expertise extends to critical projects, where she has made significant contributions.

Among her notable projects, Geetima has successfully undertaken a performance characterization project for VSDBabySoC, which involves a RISC-V core, PLL, and DAC. Additionally, she has excelled in optimizing the TCL script for STA (Static Timing Analysis), focusing on various sub-tasks to enhance efficiency.

In her optimization efforts, Geetima has tackled tasks such as reading library and verilog files, linking designs, reading SDC files, and creating directories to organize generated report files. She has also demonstrated proficiency in renaming report files and generating HTML tables from the extracted information. By meticulously analyzing hold and setup slack, start-point and end-point values, and other key parameters, she has successfully compiled comprehensive tables to showcase critical timing information.

Geetima's dedication, expertise, and ability to streamline complex processes have earned her recognition as a talented professional in the field of Electronics and Communication Engineering. Her relentless pursuit of excellence and commitment to optimizing key aspects of the field make her a valuable asset to any academic or project-oriented environment.

How will the labs be shared for the upcoming Physical Design workshop?
The labs will be shared through a virtual box image. Detailed steps on how to access and utilize the virtual box image will be provided one day prior to the start of the workshop.

What platform will be used for delivering the lectures?
The lectures for the workshop will be delivered via the VSD-IAT LMS platform. Participants will have access to the necessary course materials and can engage with the content at their own pace.

Will there be support available for questions and clarifications during the workshop?
Yes, instructors and Teaching Assistants (TAs) will be available on Slack 24/7 throughout the entire duration of the 5-day workshop. Participants can ask questions, seek clarification, and receive assistance as needed.

Is there a specific time allocated for addressing pressing issues during the workshop?
Yes, there will be a one-hour sync-up call held daily during the workshop. This call provides an opportunity for participants to address any pressing issues, discuss challenges, and receive immediate guidance and support from the instructors and TAs.

Is the workshop on a cloud-based platform? Can participants access it at their convenience?
Yes, the workshop is conducted on a cloud-based platform. Participants can log in at their convenient time, complete the lectures and labs for the day, and then log out. This allows flexibility in accessing the workshop materials and completing the required tasks based on individual schedules.

Refund Policy: Last date to apply for refund is 22 August 2023 11:59 PM IST.

Please check out : https://www.vlsisystemdesign.com/hdp/

Refund Policy: If you are not able to join workshop, Last date to apply for refund is _22 August 2023 11:59 PM IST.

For Term & Condition Policy: https://www.vlsisystemdesign.com/terms-and-conditions/

For Information drop email :vsd@vlsisystemdesign.com