Mohamed Kassem is the CTO and Co-Founder of efabless.com, the first semiconductor company applying open community innovation to all aspects of product development. Prior to launching efablesshe […]
Symposium V – Machine Intelligence in EDA/CAD applications- Let’s investigate a simple Wire Resistance Estimate (WiRE) model
This is common design automation problem which is used for estimating timing and power characteristics for analysis and implementation for many steps in ASIC flow. We will restrict our scope to physical implementation only, where known quantity is “length” of wire and resistance is predicted.
Question – Who doesn’t want a 3.5X improvement in their code size? I guess everyone wants efficient and effective improvement. Now these are just few tips to have the easy implementation of pipe-line. You are free to implement your ideas in TL-verilog, compile, simulate and see the improvements on your own. For few more tips, you might want to check out below course on “VSD – Pipelining RISC-
V with TL-verilog”
This blog is regarding abstract submission for VSDOpen2018, which is the first online conference in VLSI, that covers all aspects of semiconductor technology with prime focus to build SoC using RISC-V CPU by illustrating exciting ways using (only) opensource EDA tools.
There are multiple places, we can introduce distributed computing to timing and major motivation is to speed up the timing closure. We have to analyze timing under different range of conditions, typically quantified as modes (test mode, functional mode) and corner (PVT). The number of combinations (timing views) you have to run is typically increasing exponentially with lower nodes. That’s where you need to need to distribute timing analysis across different machines.
In start-up, many people do think commercial, while few think passion. Some of the long-lasting amazing products that you see around were built by normal, but passionate people around you. Now, Proton just fits there.Proton, A PNR tool, that can be accessed from below link:
We launched industry grade PNR EDA tool ‘Proton’ on web in front of 100 people across 7 countries, which I think, by far, has been a perfect launch for any partial open-source EDA tool.The below link has the details of the launch:
Why “integrated”? Because at lower nodes, you have to integrate other parts of the flow. Sign-off (you can see power and timing buttons below), clock tree synthesis (you can see synthesis button) must be integrated, so we have a fully integrated PnR flow that we built from day one.