Low Power Design
This is a master class in Low Power Design, taught by one of the Gurus whose work is fundamental to this field. It provides a comprehensive view of low power design from system level to device level. For the first time outside corporate settings, this course covers Voltage Aware Booleans in great detail with labs. Low Power Design for the IOT era is another new module. This course is equivalent to a 3-credit university equivalent at the graduate level. This is a front end course and needs to be followed up with a backend implantation course for VLSI students.
Principles covered in this course are:
- Low Power Design vs. Power Management
- The basic rules of Power Management
- Balancing Density-Delivery-Leakage-Lifetime
- Connecting software level activity to device level issues
- Voltage Aware Boolean Equations for CMOS
- Island ordering and how to shutdown/wakeup complex systems
- Why mobile systems explode (thermal runaway)
- Rules for verifying low power designs
- Impact of IOT on low power design
Course Learning Outcomes:
- Understand and Apply concepts of Low Power Design to Systems and Components
- Analyze and Evaluate tradeoffs in Low Power Architecture
- Understand and Apply connections between software/system level to device level
- Understand and Apply concepts of Voltage Aware Boolean Analysis to Various MV design styles
- Analyze and evaluate design hazards in Multi Voltage Design
- Apply concepts of UPF to code MultiVoltage Designs
- Understand and Apply differences between traditional and IOT low power architectures
- Understand technology direction of Low Power Designs in the future
Who this Workshop is for:
Working VLSI/Embedded System Engineers, IOT engineers, Graduate Students and Senior year B.Tech students.
Prior course work or lab work in Computer Organization, Programming and Device Physics is required.