Sign-off Timing Analysis - Basics to Advanced
Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface.
The workshop covers all the basic concepts in STA and Timing constraints. It starts with basics of Static Timing Analysis, timing paths, startpoint, endpoint and combinational logic definitions. It explains setup and hold checks, how STA tools calculate setup and hold violations. Then it slowly builds up to cover all aspects of STA like multiple types of timing paths, design rule checks, checks on async pins and clock gates. After that we go into slightly advanced topics like Time borrowing on latches, timing arcs, cell delays and models, impact of clock network on STA. Since STA and timing constraints go hand in hand the workshop covers basics of all the timing constraints that an engineer should know for STA like clock definitions, clock groups, clock characteristics, port delays and timing exceptions. Each day of the workshop is associated with labs so attendees can apply the concepts they have leant that day on practical examples and deepen their knowledge of the concepts.
Day1 Lectures1. STA Definition2. Timing Paths3. Timing path elements4. Setup & Hold Checks5. Slack Calculation6. SDC Overview7. Clocks8. Generated Clocks9. Boundary Constraints |
Day1 Labs· OpenSTA Introduction· Understanding basics of OpenSTA· Inputs to OpenSTA· Constraints creation· OpenSTA Run script |
Day2 Lectures1. Other timing checks2. Design Rule Checks3. Latch Timing4. STA Text Report |
Day2 Labs· Liberty Files and Understanding Lib Parsing· Understanding SPEF file and SPEF parsing· Understanding OpenTimer tool messages· Understanding timing reports and timing graphs |
Day3 Lectures1. Multiple Clocks2. Timing arcs and Timing Sense3. Cell Delays and Clock Network4. Setup and Hold Detailed5. STA Text Report |
Day3 Labs· Understanding full reg to reg STA analysis· Understanding Slack computation· Understanding and reviewing setup check report |
Day4 Lectures1. Crosstalk and Noise2. Operating modes and other variations3. Clock Gating Checks4. Checks on Async Pins |
Day4 Labs· Understanding clock gating check· Understanding Async pin checks |
Day5 Lectures1. Clock groups2. Clock properties3. Timing exceptions4. Multiple modes |
Day5 Labs· Revisit slack computation· Understand CRPR· ECO insertion |
- OpenSTA
- Virtual Coach platform with expert instructor guidance
- Cloud-based dedicated Virtual Machine to perform Design labs
- Intelligent Assessment Technology (IAT) and Project allocation
- 24 hours Lab access for 5 days and Instructor assistance on demand
- Run EDA scripts and Timing analysis reports on platform.
Instructor Profile:
Vikas Sachdeva is a semiconductor design professional with more than 17 years of experience in the VLSI Industry. He has worked in design, development, and deployment of multiple static and constraints products.He is currently the Director of Product Strategy and Business Development at Real Intent.
At Real Intent, He is Driving Product Strategy for the Key Static Signoff Products. He is also working as an Advisor, Tech and VLSI Coach and Trainer for vlsideepdive in his spare time.
★ Seasoned Product Leader with multiple years of driving product strategy & product management
★ Highly effective product manager with strong customer focus
★ Tech and VLSI Coach & Trainer for hi-tech, product management, general management and growth hacking courses
★ Startup Advisor for multiple startups at pre-seed stage
★ Always pushing for innovation
★ Youtuber driving youtube channel of vlsideepdive
★ Speaker at multiple conferences and vlsideepdive events
★ Professional with over 17 years of technology management experience representing various stages of product life cycle including product development, product management, implementation management and product support
★ Extensive experience developing and validating positioning, messaging, competition, segmentation, and go-to-market strategy for a fast-paced, high growth technology market
★ Strong tech industry experience in understanding, development, and deployment of solutions for complex problems
VSD has been conducting Hardware design programs for 3 years now and seen some amazing results, like great opensource IPs, amazing solutions for power analysis, innovations using Sky130 PDKs and close to 50+ silicon ready designs awaiting tape-outs. The reason for the success of HDP is the level of freedom which it allows for innovation.
VSD follows a strict 5-stage process, which is a typical practice in top semi-conductor design companies, thereby, providing an experience which is similar work working for a design company. That is the reason this program is recommended by some top industry professionals.
Please check out : https://www.vlsisystemdesign.com/hdp/
Participants should Know basics of setup and hold time, meaning of flops, gates latches, also have some idea about vlsi design flow
- Students who want to understand STA, and gain some experience in the field
- Students/ young Professionals working in other fields of vlsi wanting to switch to this field
- Experienced professionals wanting to brush up their skills, prepare for interviews or want to learn advanced concepts of sta
- Professionals already working in STA/physical design/backend wanting to upskill
Refund Policy: Last date to apply for refund is 17 February 2023 11:59 PM IST.
Refund Policy: If you are not able to join workshop, Last date to apply for refund is 17 February 2023 11:59 PM IST.
For Term & Condition Policy: https://www.vlsisystemdesign.com/terms-and-conditions/
