Design Compiler is an Advanced Synthesis Tool used by leading semiconductor companies across world.

Synthesis of logic circuits plays a crucial role in optimizing the logic and achieving the targeted performance, area and power goals of an IC.

Understanding the fundamentals of design are very important to give the correct inputs to the tool to achieve the best-in-class netlist quality.

This workshop explores the following aspects,

• Design fundamentals
• Setting up DC for synthesis
• Understanding STA
• Understanding and writing the Synopsys Design Constraints [SDC].
• Analyzing the quality of netlist synthesized.

SDCs [Synopsys Design Constraints] are standardized way of constraining the design across the EDA [Electronic Design Automation] tools. Understanding the SDCs helps to work across the EDA implementation tools.

Day 1  : Introduction to Logic Synthesis

• Introduction to Design Compiler
• what is Logic Synthesis ,
• What is netlist , libraries ,
• TCL Quick refresher
• What is DC and how to launch DC ,
• What are the inputs needed to load the design in DC ,
• Loading a basic design in DC ,
• Writing out a basic NL and DDC

Day 2:

• Basics of STA ,
• Delays
• Timing Arcs
• Constraining the Design
• What is STA , setup , hold quick recap .
• What are constraints
• Constraining the Reg2Reg , Reg2IO , IO2Reg Paths
• Input transition and OutputLoad and its effects on IO delays.

Day 3: Advanced Constraints

• Clock Skew and Clock Jitter, its modelling in DC
• Writing SDCs [Synopsys Design Constraints]
• Creating Clocks
• Querying Cells
• Specifying IO Delays
• Specifying Clock Waveforms
• Generated Clocks
• Multi Clock Design
• False Paths

Day 4:

• Optimizations in Synthesis
• Combinational Logic Optimization
• Boolean Reduction
• Constant Propagation
• Synthesis Directives
• Synopsys full_case
• Synopsys parallel_case
• Sequential Logic Optimization
• Sequential Constant
• Retiming / Pipelining

Day5 :

• Checking Netlist Quality and Generating Reports
• Generating Timing Reports
• max_paths
• nworst
• Boundary Optimizations
• check_design
• check_timing
• HFN (High Fanout Nets)

• Design Compiler,
• Iverilog Languages
• Verilog,
• TCL

1. Virtual Coach platform with expert instructor guidance
2. Cloud-based dedicated Virtual Machine to perform Design labs
3. Intelligent Assessment Technology (IAT) and Project allocation
4. 24 hours Lab access for 5 days and Instructor assistance on demand
5. Run EDA scripts, evaluate VLSI layout and Timing analysis reports on platform.

Instructor Profile:

Kunal Ghosh, co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd., Kunal pioneers in the field of online open-source EDA (qflow & openroad)/open-source hardware (specially RISC-V) design and learning. Currently, Kunal owns around 32 high-quality VLSI online courses in and around open-source EDA/hardware, which is being consumed by around 28700+ students around 141 countries. Apart from trainings, Kunal has also worked with IIT Madras and IIT Guwahati on open-source activities and design projects. Currently, Kunal and his team are working on developing high quality open-source Analog/Digital IP’s which would be first one’s in the field of open-source hardware design. Prior to VSD, Kunal has worked with Qualcomm and Cadence, in field of SoC design. Kunal has done his Masters at IIT Bombay in field of VLSI & Nano-electronics, with specialisation in Sub-100nm Electron Beam LithographyOptimisation techniques

Refund Policy: If you are not able to join workshop, Last date to apply for refund is  20 September 2021 11:59 PM IST.

For Term & Condition Policy: https://www.vlsisystemdesign.com/terms-and-conditions/

Hardware design program will help you unleash the innovator inside you which the world and pandemic has been holding you back from

In just 10-weeks, you will explore the researcher within you. You will:

→ AND MUCH MORE

Please check out : https://www.vlsisystemdesign.com/hdp/