Hi “Pictures speak it all” Finally, we all did it – VSDOpen – first ever online VLSI conference. Very close to a real one – […]
Timing-driven optimization is imperative for the success of closure flows. The optimization engine applies changes to the design and estimates circuit delays quickly and accurately to improve timing, area, and power performance. This procedure is inherently complex and computationally challenging.
A working chip is all using opensource EDA tools (no more license fee). Of course, its taped-out in 180nm technology. But who knows, this might be just the beginning. Upcoming blogs will talk more about the commercial angle of this. Let’s see how it is going to benefit student/professionals/innovators community
our company to move from LMS (Learning Management System) to EMS (EDA Management System), and finally we envision, very soon to be in DMS (Design Management System).Talking about ‘vsdflow’, it’s the main theme of this paper, and if I had to describe it in few lines, it’s a ‘plug and play (PnP)’ EDA management system, built for chip designers to implement their ideas and convert to GDSII.
A PPA card like the above, is something which every VLSI engineer should be carrying like a business card. Why? Right from RTL to synthesis to PNR to signoff, we do things like upsize, downsize, VT swap, and many more, and all these factors impacts or tweaks your design PPA in one way or the other.
Let’s take an example of ‘downsize’
the flowchart is what you need to understand just to be an expert in the field of VLSI and semiconductors. Every topic shown in above image is a field, and every topic has a beautiful physics behind it, which when blended with tools in a video course, becomes a master-piece
read_sdc is been considered as a very critical command in EDA world, as this is the command which defines your specifications, and if not written and interpreted correctly, can lead a huge delay in tapeout cycle.
Looks like a very popular EDA command, isn’t it? Yes, it is. Well, this command actually is just an interface for users. At the back-end, […]
Never really found a chance to properly introduce myself and my background to all of you. So here it is… My name is Kunal Ghosh […]
Its a glimpse of physical design flow, static timing analysis, static circuit simulation, dynamic circuit simulations, leakage & switching power concepts, crosstalk glitch & delta delay concepts and basic delay of a cell.