13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core

It was also a real testament to Nicholas’s thirst for knowledge and the outside-the-box thinking of his home-schooling parents, Rasa and Mike. Having a 13-year-old of my own, I was particularly impressed by Nicholas’s willingness to put himself out there, asking questions and joining Zoom calls (not to mention his familiarity with Linux). I’ve since learned that Nicholas has been awarded in spelling bees and math competitions and is an expert at solving the Rubik’s Cube. Somehow, I’m not surprised.

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150+ students have decided to upskill in VLSI

And that’s where VSD must play an especially important role to bring in latest and greatest VLSI skills to you, atleast in the field of open-source hardware. VSD owes a lot to VLSI community and hence has planned 3 exclusive cloud lab-based VLSI workshops on 3 important topics, with top 3 expert instructors from around globe,  having more than 2 decades of experience – Tim Edwards, Steve Hoover, and Prof. Mohamed Shalan

Open-source EDA tool development with lab exercises using Sky130 pdk’s by Google/Skywater
RISC-V micro-architecture using transaction level – Verilog with lab exercises on Makerchip Platform
SoC and Physical Design using Automated RTL2GDS OpenLANE tool with lab exercises using demo design and Sky130 pdk’s.

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Let Knowledge Win

Trust me – KNOWLEDGE TRANSFER to students is MOST SATISFYING feeling.  

The key thing over here – It must be short and crisp so everyone can enjoy the topic. These are memorable times, where everyone needs to do their bit to fight a battle against an unknown enemy. You need not make new slides, you are free to present your personal/company slides, provided it’s available on public platform.

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Paper 3: Coverage Driven Functional Verification on RISC-V Cores

Design Verification is critical to proving functional correct- ness and establishing confidence in a design. Several stud- ies from industry and academia, particularly over the course of the last two decades, have explored various verifica- tion methodologies that fall somewhere between dynamic or purely static formal approaches.
System-on-Chips (SoCs) today have become extremely complex structures housing heavily optimized cores, count- less peripherals, and large interconnect fabrics. Even re- stricting ourselves to just verifying the microprocessor, the state space to be verified is enormous and cannot be exhaus- tively explored in any finite amount of time. Manually writ- ten tests, while effective at capturing some complexities of design intent, suffer from the fact that they are expensive in cost and time required to develop them. Random stimulus methods perform better because they eventually cover many cases. Most new ideas in dynamic verification over the last two decades have largely been towards semi formal verifi- cation methodologies such as coverage driven verification and constrained test generation. In this paper, we explore an approach to dynamic functional verification that we use at the RISE lab, IIT Madras for the verification of the RISC-V based Shakti cores.

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RISC-V enters India and VSD personally invite you…

We would like to invite you to attend one of the SiFive & Open-Silicon Tech Symposiums taking place at six different locations throughout India in August. See map in below image for exact locations and date of events.

I would be presenting a very important tutorial, which closely connects open-source ISA implementation to open-source EDA tools – “How to design complex RISC-V SoC with open-source EDA tools and time to productize design ideas?”

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From concept to algorithm – RISC-V floating point addition

First thing which comes in the title is “concept”, which is the simple one. It says, if I want to add 2 floating-point numbers, I simply add them. Second, “algorithm” is the details for a computer, how it will add 2 floating-point numbers.Third, which is “RISC-V”, which deals with binary numbers, describes how can you use same concept and algorithm to do a “binary floating-point addition”

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